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? 2012 microchip technology inc. preliminary ds41624b pic16(l)f1512/1513 data sheet 28-pin flash microcontrollers with xlp technology
ds41624b-page 2 preliminary ? 2012 microchip technology inc. information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mxdev, mxlab, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. analog-for-the-digital age, app lication maestro, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, total endurance, tsharc, uniwindriver, wiperlock and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of microchip technology incorporated in the u.s.a. all other trademarks mentioned herein are property of their respective companies. ? 2012, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620763483 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protection feature. all of these methods, to our knowledge, require using the microchip produc ts in a manner outside the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer c an guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvi ng the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
? 2012 microchip technology inc. preliminary ds41624b-page 3 high-performance risc cpu: ? c compiler optimized architecture ? only 49 instructions ? up to 7 kbytes linear program memory addressing ? up to 256 bytes linear data memory addressing ? operating speed: - dc ? 20 mhz clock input @ 2.5v - dc ? 16 mhz clock input @ 1.8v - dc ? 200 ns instruction cycle ? interrupt capability with automatic context saving ? 16-level deep hardware stack with optional overflow/underflow reset ? direct, indirect and relative addressing modes: - two full 16-bit file select registers (fsrs) - fsrs can read program and data memory flexible oscillator structure: ? 16 mhz internal oscillator block: - factory calibrated to 1%, typical - software selectable frequency range from 16 mhz to 31 khz ? 31 khz low-power internal oscillator ? external oscillator block with: - four crystal/resonator modes up to 20 mhz - three external clock modes up to 20 mhz ? fail-safe clock monitor: - allows for safe shutdown if peripheral clock stops ? two-speed oscillator start-up ? oscillator start-up timer (ost) analog features: ? analog-to-digital converter (adc): - 10-bit resolution - up to 17 channels - special event triggers - conversion available during sleep - hardware capacitive voltage divider (cvd) - double sample conversions - two result registers - inverted acquisition - 7-bit pre-charge timer - 7-bit acquisition timer - two guard ring output drives - adjustable sample and hold capacitor array ? voltage reference module: - fixed voltage reference (fvr) with 1.024v, 2.048v and 4.096v output levels ? integrated temperature indicator extreme low-power management pic16lf1512/3 with xlp: ? sleep mode: 20 na @ 1.8v, typical ? watchdog timer: 300 na @ 1.8v, typical ? secondary oscillator: 600 na @ 32 khz, 1.8v, typical ? operating current: 30 ? a/mhz @ 1.8v, typical special microcontroller features: ? operating voltage range: - 2.3v-5.5v (pic16f1512/3) - 1.8v-3.6v (pic16lf1512/3) ? self-programmable under software control ? power-on reset (por) ? power-up timer (pwrt) ? programmable low-power brown-out reset (lpbor) ? extended watchdog timer (wdt) ? in-circuit serial programming? (icsp?) via two pins ? in-circuit debug (icd) via two pins ? enhanced low-voltage programming (lvp) ? programmable code protection ? low-power sleep mode ? 128 bytes high-endurance flash: - 100,000 write flash endurance (minimum) peripheral highlights: ? up to 25 i/o pins (1 input-only pin): - high current sink/source 25 ma/25 ma - individually programmable weak pull-ups - individually programmable interrupt-on-change (ioc) pins ? timer0: 8-bit timer/counter with 8-bit prescaler ? enhanced timer1: - 16-bit timer/counter with prescaler - external gate input mode - low-power 32 khz secondary oscillator driver ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? two capture/compare (ccp) modules: ? master synchronous serial port (mssp) with spi and i 2 c tm with: - 7-bit address masking - smbus/pmbus tm compatibility ? enhanced universal synchronous asynchronous receiver transmitter (eusart) module: - rs-232, rs-485 and lin compatible - auto-baud detect - auto-wake-up on start pic16(l)f1512/3 28-pin flash microcontroll ers with xlp technology
pic16(l)f1512/3 ds41624b-page 4 preliminary ? 2012 microchip technology inc. pic16(l)f151x/152x family types figure 1: 28-pin spdip, soic, ssop package diagram for pic16(l)f1512/3 device data sheet index program memory flash (words) data sram (bytes) i/o?s (2) adc timers (8/16-bit) eusart mssp (i 2 c?/spi) ccp debug (1) xlp 10-bit (ch) advanced control pic16(l)f1512 (1) 2048 128 25 17 y 2/1 1 1 2 i y pic16(l)f1513 (1) 4096 256 25 17 y 2/1 1 1 2 i y pic16(l)f1516 (2) 8192 512 25 17 n 2/1 1 1 2 i y pic16(l)f1517 (2) 8192 512 36 28 n 2/1 1 1 2 i y pic16(l)f1518 (2) 16384 1024 25 17 n 2/1 1 1 2 i y pic16(l)f1519 (2) 16384 1024 36 28 n 2/1 1 1 2 i y pic16(l)f1526 (3) 8192 768 54 30 n 6/3 2 2 10 i y pic16(l)f1527 (3) 16384 1536 54 30 n 6/3 2 2 10 i y note 1: i - debugging, integrated on chip; h - debugging, requires debug header. 2: one pin is input-only. data sheet index: (unshaded devices are described in this document.) 1: future product pic16(l)f1512/13 data sheet, 28-pin flash, 8-bit microcontrollers. 2: ds41452 pic16(l)f1516/7/8/9 data sheet, 28/40/44-pin flash, 8-bit mcus. 3: ds41458 pic16(l)f1526/27 data sheet, 64-pin flash, 8-bit mcus. 28-pin spdip, soic, ssop pic16f1512/3 pic16lf1512/3 1 2 3 4 5 6 7 8 9 10 v pp /mclr /re3 ra0 ra1 ra2 ra3 ra4 ra5 rb6/icspclk/icdclk rb5 rb4 rb3 rb2 rb1 rb0 v dd v ss 11 12 13 14 15 16 17 18 19 20 28 27 26 25 24 23 22 21 v ss ra7 ra6 rc0 rc1 rc2 rc3 rc5 rc4 rc7 rc6 rb7/icspdat/icddat
? 2012 microchip technology inc. preliminary ds41624b-page 5 pic16(l)f1512/3 figure 2: 28-pin uqfn (4x4) packag e diagram for pic16(l)f1512/3 2 3 6 1 18 19 20 21 15 7 16 17 rc0 5 4 rb7/icspdat/icddat rb6/icspclk/icdclk rb5 rb4 rb3 rb2 rb1 rb0 v dd v ss rc7 rc6 rc5 rc4 re3/mclr /v pp ra0 ra1 ra2 ra3 ra4 ra5 v ss ra7 ra6 rc1 rc2 rc3 9 10 13 8 14 12 11 27 26 23 28 22 24 25 pic16f1512/3 pic16lf1512/3 28-pin uqfn
pic16(l)f1512/3 ds41624b-page 6 preliminary ? 2012 microchip technology inc. table 1: 28-pin allocation table (pic16(l)f1512/3) i/o 28-pin spdip, soic, ssop 28-pin uqfn a/d timers ccp eusart mssp interrupt pull-up basic ra0 2 27 an0 ? ? ? ss (2) ? ? ? ra1328an1 ? ??? ?? ? ra2 4 1 an2 ? ? ? ? ? ? ? ra3 5 2 an3/v ref + ? ??? ?? ? ra4 6 3 ? t0cki ? ? ? ? ? ? ra5 7 4 an4 ? ? ? ss (1) ?? v cap ra6 10 7 ? ? ? ? ? ? ? osc2/clkout ra7 9 6 ? ? ? ? ? ? ? osc1/clkin rb0 21 18 an12 ? ? ? ? int/ioc y ? rb1 22 19 an10 ? ? ? ? ioc y ? rb2 23 20 an8 ? ? ? ? ioc y ? rb3 24 21 an9 ? ccp2 (2) ??iocy ? rb4 25 22 an11 adout ? ? ? ? ioc y ? rb5 26 23 an13 t1g ? ? ? ioc y ? rb6 27 24 adgrda ? ? ? ? ioc y icspclk/icdclk rb7 28 25 adgrdb ? ? ? ? ioc y icspdat/icddat rc0 11 8 ? sosco/t1cki ? ? ? ? ? ? rc1 12 9 ? sosci ccp2 (1) ?? ?? ? rc2 13 10 an14 ? ccp1 ? ? ? ? ? rc3 14 11 an15 ? ? ? sck/scl ? ? ? rc4 15 12 an16 ? ? ? sdi/sda ? ? ? rc5 16 13 an17 ? ? ? sdo ? ? ? rc6 17 14 an18 ? ? tx/ck ? ? ? ? rc7 18 15 an19 ? ? rx/dt ? ? ? ? re3 1 26 ? ? ? ? ? ? y mclr /v pp v dd 20 17 ? ? ? ? ? ? ? ? v ss 8,19 5,16 ? ? ? ? ? ? ? ? nc ? ? ? ? ? ? ? ? ? ? note 1: peripheral pin location selected using apfcon register. default location. 2: peripheral pin location selected using apfcon register. alternate location.
? 2012 microchip technology inc. preliminary ds41624b-page 7 pic16(l)f1512/3 table of contents 1.0 device overview ............................................................................................................. ............................................................. 9 2.0 enhanced mid-range cpu ...................................................................................................... ................................................... 13 3.0 memory organization ......................................................................................................... ........................................................ 15 4.0 device configuration ........................................................................................................ .......................................................... 37 5.0 oscillator module (with fail-safe clock monitor)............................................................................ ........................................... 43 6.0 resets ...................................................................................................................... .................................................................. 59 7.0 interrupts .................................................................................................................. .................................................................. 67 8.0 power-down mode (sleep) ..................................................................................................... ................................................... 79 9.0 low dropout (ldo) voltage regulator ......................................................................................... ............................................. 83 10.0 watchdog timer (wdt) ....................................................................................................... ...................................................... 85 11.0 flash program memory control ............................................................................................... .................................................. 89 12.0 i/o ports .................................................................................................................. ................................................................. 105 13.0 interrupt-on-change ........................................................................................................ ........................................................ 121 14.0 fixed voltage reference (fvr) .............................................................................................. ................................................. 125 15.0 temperature indicator module ............................................................................................... .................................................. 127 16.0 analog-to-digital converter (adc) module ................................................................................... ........................................... 129 17.0 timer0 module .............................................................................................................. ........................................................... 163 18.0 timer1 module with gate control............................................................................................ ................................................. 167 19.0 timer2 module .............................................................................................................. ........................................................... 179 20.0 master synchronous serial port (mssp) module ............................................................................... ..................................... 183 21.0 capture/compare/pwm modules ................................................................................................ ............................................ 237 22.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) .................................................. ............. 247 23.0 in-circuit serial programming? (icsp?) ..................................................................................... .......................................... 275 24.0 instruction set summary .................................................................................................... ...................................................... 279 25.0 electrical specifications.................................................................................................. .......................................................... 293 26.0 dc and ac characteristics graphs and charts ................................................................................ ....................................... 321 27.0 development support........................................................................................................ ....................................................... 323 28.0 packaging information...................................................................................................... ........................................................ 327 the microchip web site ......................................................................................................... ............................................................ 345 customer change notification service ........................................................................................... ................................................... 345 customer support............................................................................................................... ............................................................... 345 reader response ................................................................................................................ .............................................................. 346 product identification system .................................................................................................. .......................................................... 347
pic16(l)f1512/3 ds41624b-page 8 preliminary ? 2012 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the be st documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regardi ng this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2012 microchip technology inc. preliminary ds41624b-page 9 pic16(l)f1512/3 1.0 device overview the pic16(l)f1512/3 are described within this data sheet. they are available in 28-pin packages. figure 1-1 shows a block diagram of the pic16(l)f1512/3 devices. table 1-2 shows the pinout descriptions. reference tab l e 1 - 1 for peripherals available per device. table 1-1: device peripheral summary peripheral pic16(l)f1512 pic16(l)f1513 analog-to-digital converter (adc) fixed voltage reference (fvr) temperature indicator capture/compare/pwm modules ccp1 ccp2 eusarts eusart master synchronous serial ports mssp timers timer0 timer1 timer2
pic16(l)f1512/3 ds41624b-page 10 preliminary ? 2012 microchip technology inc. figure 1-1: pic16(l)f1512/3 block diagram portb timer2 mssp timer0 ccp2 adc 10-bit ccp1 note 1: see applicable chapters for more information on peripherals. 2: see ta b l e 1 - 1 for peripherals available on specific devices. cpu program flash memory porta ram timing generation intrc oscillator mclr ( figure 2-1 ) timer1 osc1/clkin osc2/clkout fvr portc porte te m p . indicator eusart
? 2012 microchip technology inc. preliminary ds41624b-page 11 pic16(l)f1512/3 table 1-2: pic16(l)f1512/3 pinout description name function input type output type description ra0/an0/ss (2) ra0 ttl cmos general purpose i/o. an0 an ? a/d channel 0 input. ss st ? slave select input. ra1/an1 ra1 ttl cmos general purpose i/o. an1 an ? a/d channel 1 input. ra2/an2 ra2 ttl cmos general purpose i/o. an2 an ? a/d channel 2 input. ra3/an3/v ref + ra3 ttl cmos general purpose i/o. an3 an ? a/d channel 3 input. v ref + an ? a/d positive voltage reference input. ra4/t0cki ra4 ttl cmos general purpose i/o. t0cki st ? timer0 clock input. ra5/an4/ss (1) /v cap ra5 ttl cmos general purpose i/o. an4 an ? a/d channel 4 input. ss st ? slave select input. v cap power power filter capacitor for voltage regulator (pic16f1512/3 only). ra6/osc2/clkout ra6 ttl cmos general purpose i/o. osc2 ? xtal crystal/resonator (lp, xt, hs modes). clkout ? cmos f osc /4 output. ra7/osc1/clkin ra7 ttl cmos general purpose i/o. osc1 xtal ? crystal/resonator (lp, xt, hs modes). clkin st ? external clock input (ec mode). rb0/an12/int rb0 ttl cmos general purpose i/o with ioc and wpu. an12 an ? a/d channel 12 input. int st ? external interrupt. rb1/an10 rb1 ttl cmos general purpose i/o with ioc and wpu. an10 an ? a/d channel 10 input. rb2/an8 rb2 ttl cmos general purpose i/o with ioc and wpu. an8 an ? a/d channel 8 input. rb3/an9/ccp2 (2) rb3 ttl cmos general purpose i/o with ioc and wpu. an9 an ? a/d channel 9 input. ccp2 st cmos capture/compare/pwm 2. rb4/an11/adout rb4 ttl cmos general purpose i/o with ioc and wpu. an11 an ? a/d channel 11 input. adout cmos ? a/d with cvd output. rb5/an13/t1g rb5 ttl cmos general purpose i/o with ioc and wpu. an13 an ? a/d channel 13 input. t1g st ? timer1 gate input. rb6/icspclk/adgrda rb6 ttl cmos general purpose i/o with ioc and wpu. icspclk st cmos in-circuit data i/o. adgrda ? cmos guard ring output a. legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: peripheral pin location selected using apfcon register ( register 12-1) . default location. 2: peripheral pin location selected using apfcon register ( register 12-1) . alternate location.
pic16(l)f1512/3 ds41624b-page 12 preliminary ? 2012 microchip technology inc. rb7/icspdat/adgrdb rb7 ttl cmos general purpose i/o with ioc and wpu. icspdat st cmos icsp? data i/o. adgrdb ? cmos guard ring output b. rc0/sosco/t1cki rc0 st cmos general purpose i/o. sosco ? xtal secondary oscillator connection. t1cki st ? timer1 clock input. rc1/sosci/ccp2 (1) rc1 st cmos general purpose i/o. sosci ? xtal secondary oscillator connection. ccp2 st cmos capture/compare/pwm 2. rc2/an14/ccp1 rc2 st cmos general purpose i/o. an14 an ? a/d channel 14 input. ccp1 st cmos capture/compare/pwm 1. rc3/an15/sck/scl rc3 st cmos general purpose i/o. an15 an ? a/d channel 15 input. sck st cmos spi clock. scl i 2 c? od i 2 c? clock. rc4/an16/sdi/sda rc4 st cmos general purpose i/o. an16 an ? a/d channel 16 input. sdi st ? spi data input. sda i 2 c? od i 2 c? data input/output. rc5/an17/sdo rc5 st cmos general purpose i/o. an17 an ? a/d channel 17 input. sdo ? cmos spi data output. rc6/an18/tx/ck rc6 st cmos general purpose i/o. an18 an ? a/d channel 18 input. tx ? cmos usart asynchronous transmit. ck st cmos usart synchronous clock. rc7/an19/rx/dt rc7 st cmos general purpose i/o. an19 an ? a/d channel 19 input. rx st ? usart asynchronous input. dt st cmos usart synchronous data. re3/mclr /v pp re3 st ? general purpose input with wpu. mclr st ? master clear with internal pull-up. v pp hv ? programming voltage. v dd v dd power ? positive supply. v ss v ss power ? ground reference. table 1-2: pic16(l)f1512/3 pinout description (continued) name function input type output type description legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: peripheral pin location selected using apfcon register ( register 12-1) . default location. 2: peripheral pin location selected using apfcon register ( register 12-1) . alternate location.
? 2012 microchip technology inc. preliminary ds41624b-page 13 pic16(l)f1512/3 2.0 enhanced mid-range cpu this family of devices contain an enhanced mid-range 8-bit cpu core. the cpu has 49 instructions. interrupt capability includes automatic context saving. the hardware stack is 16 levels deep and has overflow and underflow reset capability. direct, indirect, and relative addressing modes are available. two file select registers (fsrs) provide the ability to read program and data memory. ? automatic interrupt context saving ? 16-level stack with overflow and underflow ? file select registers ? instruction set 2.1 automatic interrupt context saving during interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. this saves stack space and user code. see section 7.5 ?automatic context saving? , for more information. 2.2 16-level stack with overflow and underflow these devices have an external stack memory 15 bits wide and 16 words deep. a stack overflow or under- flow will set the appropriate bit (stkovf or stkunf) in the pcon register and, if enabled, will cause a software reset. see section 3.4 ?stack? for more details. 2.3 file select registers there are two 16-bit file select registers (fsr). fsrs can access all file registers and program memory, which allows one data pointer for all memory. when an fsr points to program memory, there is one additional instruction cycle in instructions using indf to allow the data to be fetched. general purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. there are also new instructions to support the fsrs. see section 3.5 ?indirect addressing? for more details. 2.4 instruction set there are 49 instructions for the enhanced mid-range cpu to support the features of the cpu. see section 24.0 ?instruction set summary? for more details.
pic16(l)f1512/3 ds41624b-page 14 preliminary ? 2012 microchip technology inc. figure 2-1: core block diagram data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 12 addr mux fsr reg status reg mux alu power-up timer oscillator start-up timer power-on reset watchdog timer instruction decode & control timing generation osc1/clkin osc2/clkout v dd 8 8 brown-out reset 12 3 v ss internal oscillator block configuration data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 addr mux fsr reg status reg mux alu w reg instruction decode & control timing generation v dd 8 8 3 v ss internal oscillator block configuration 15 data bus 8 14 program bus instruction reg program counter 16-level stack (15-bit) direct addr 7 ram addr addr mux indirect addr fsr0 reg status reg mux alu instruction decode and control timing generation v dd 8 8 3 v ss internal oscillator block configuration flash program memory ram fsr reg fsr reg fsr1 reg 15 15 mux 15 program memory read (pmr) 12 fsr reg fsr reg bsr reg 5
? 2012 microchip technology inc. preliminary ds41624b-page 15 pic16(l)f1512/3 3.0 memory organization these devices contain the following types of memory: ? program memory - configuration words - device id -user id - flash program memory ? data memory - core registers - special function registers - general purpose ram - common ram the following features are associated with access and control of program memory and data memory: ? pcl and pclath ?stack ? indirect addressing 3.1 program memory organization the enhanced mid-range core has a 15-bit program counter capable of addressing a 32k x 14 program memory space. table 3-1 shows the memory sizes implemented for these devices. accessing a location above these boundaries will cause a wrap-around within the implemented memory space. the reset vector is at 0000h and the interrupt vector is at 0004h (see figure 3-1 and figure 3-2 ). table 3-1: device sizes and addresses device program memory space (words) last program memory address pic16f1512 pic16lf1512 2,048 07ffh pic16f1513 pic16lf1513 4,096 0fffh
pic16(l)f1512/3 ds41624b-page 16 preliminary ? 2012 microchip technology inc. figure 3-1: program memory map and stack for pic16(l)f1512 parts figure 3-2: program memory map and stack for pic16(l)f1513 parts pc<14:0> 15 0000h 0004h stack level 0 stack level 15 reset vector interrupt vector stack level 1 0005h on-chip program memory page 0 07ffh wraps to page 0 wraps to page 0 wraps to page 0 0800h call , callw return , retlw interrupt, retfie rollover to page 0 rollover to page 0 7fffh pc<14:0> 15 0000h 0004h stack level 0 stack level 15 reset vector interrupt vector call , callw return , retlw stack level 1 0005h on-chip program memory page 0 07ffh rollover to page 0 0800h 0fffh 1000h 7fffh page 1 rollover to page 1 interrupt, retfie
? 2012 microchip technology inc. preliminary ds41624b-page 17 pic16(l)f1512/3 3.1.1 reading program memory as data there are two methods of accessing constants in program memory. the first method is to use tables of retlw instructions. the second method is to set an fsr to point to the program memory. 3.1.1.1 retlw instruction the retlw instruction can be used to provide access to tables of constants. the recommended way to create such a table is shown in example 3-1 . example 3-1: retlw instruction the brw instruction makes this type of table very simple to implement. if your code must remain portable with previous generations of microcontrollers, then the brw instruction is not available so the older table read method must be used. 3.1.1.2 indirect read with fsr the program memory can be accessed as data by setting bit 7 of the fsrxh register and reading the matching indfx register. the moviw instruction will place the lower eight bits of the addressed word in the w register. writes to the program memory cannot be performed via the indf registers. instructions that access the program memory via the fsr require one extra instruction cycle to complete. example 3-2 demonstrates accessing the program memory via an fsr. the high directive will set bit<7> if a label points to a location in program memory. example 3-2: accessing program memory via fsr constants brw ;add index in w to ;program counter to ;select data retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ;? lots of code? movlw data_index call constants ;? the constant is in w constants retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ;? lots of code? movlw low constants movwf fsr1l movlw high constants movwf fsr1h moviw 0[fsr1] ;the program memory is in w
pic16(l)f1512/3 ds41624b-page 18 preliminary ? 2012 microchip technology inc. 3.2 data memory organization the data memory is partitioned in 32 memory banks with 128 bytes in a bank. each bank consists of ( figure 3-3 ): ? 12 core registers ? 20 special function registers (sfr) ? up to 80 bytes of general purpose ram (gpr) ? 16 bytes of common ram the active bank is selected by writing the bank number into the bank select register (bsr). unimplemented memory will read as ? 0 ?. all data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two file select registers (fsr). see section 3.5 ?indirect addressing? for more information. data memory uses a 12-bit address. the upper seven bits of the address define the bank address and the lower five bits select the registers/ram in that bank. 3.2.1 core registers the core registers contain the registers that directly affect the basic operation. the core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0bh/x8bh). these registers are listed below in ta b l e 3 - 2 . for detailed information, see tab l e 3 - 8 . table 3-2: core registers addresses bankx x00h or x80h indf0 x01h or x81h indf1 x02h or x82h pcl x03h or x83h status x04h or x84h fsr0l x05h or x85h fsr0h x06h or x86h fsr1l x07h or x87h fsr1h x08h or x88h bsr x09h or x89h wreg x0ah or x8ah pclath x0bh or x8bh intcon
? 2012 microchip technology inc. preliminary ds41624b-page 19 pic16(l)f1512/3 3.2.1.1 status register the status register, shown in register 3-1 , contains: ? the arithmetic status of the alu ? the reset status the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as ? 000u u1uu ? (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bits. for other instructions not affecting any status bits (refer to section 24.0 ?instruction set summary? ). note 1: the c and dc bits operate as borrow and digit borrow out bits, respectively, in subtraction. register 3-1: status: status register u-0 u-0 u-0 r-1/q r-1/q r/w-0/u r/w-0/u r/w-0/u ? ? ? to pd zdc (1) c (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7-5 unimplemented: read as ? 0 ? bit 4 to : time-out bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/digit borrow bit (1) 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit (1) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand.
pic16(l)f1512/3 ds41624b-page 20 preliminary ? 2012 microchip technology inc. 3.2.2 special function register the special function registers are registers used by the application to control the desired operation of peripheral functions in the device. the special function registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0ch/x8ch through x1fh/x9fh). the registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet. 3.2.3 general purpose ram there are up to 80 bytes of gpr in each data memory bank. the special function registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0ch/x8ch through x1fh/x9fh). 3.2.3.1 linear access to gpr the general purpose ram can be accessed in a non-banked method via the fsrs. this can simplify access to large memory structures. see section 3.5.2 ?linear data memory? for more information. 3.2.4 common ram there are 16 bytes of common ram accessible from all banks. figure 3-3: banked memory partitioning 3.2.5 device memory maps the memory maps for pic16(l)f1512/3 are as shown in table 3-4 through ta b l e 3 - 7 . 0bh 0ch 1fh 20h 6fh 70h 7fh 00h common ram (16 bytes) general purpose ram (80 bytes maximum) core registers (12 bytes) special function registers (20 bytes maximum) memory region 7-bit bank offset
? 2012 microchip technology inc. preliminary ds41624b-page 21 pic16(l)f1512/3 table 3-3: pic16(l)f1512 memory map (banks 0-7) legend: = unimplemented data memory locations, read as ? 0 ?. note 1: pic16f1512 only. bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 000h core registers ( ta b l e 3 - 2 ) 080h core registers ( ta b l e 3 - 2 ) 100h core registers ( table 3-2 ) 180h core registers ( table 3-2 ) 200h core registers ( table 3-2 ) 280h core registers ( table 3-2 ) 300h core registers ( table 3-2 ) 380h core registers ( table 3-2 ) 00bh 08bh 10bh 18bh 20bh 28bh 30bh 38bh 00ch porta 08ch trisa 10ch lata 18ch ansela 20ch ? 28ch ? 30ch ? 38ch ? 00dh portb 08dh trisb 10dh latb 18dh anselb 20dh wpub 28dh ? 30dh ? 38dh ? 00eh portc 08eh trisc 10eh latc 18eh anselc 20eh ?28eh ?30eh ?38eh ? 00fh ?08fh ?10fh ?18fh ?20fh ?28fh ?30fh ?38fh ? 010h porte 090h trise 110h ?190h ? 210h wpue 290h ? 310h ? 390h ? 011h pir1 091h pie1 111h ? 191h pmadrl 211h ssp1buf 291h ccpr1l 311h ? 391h ? 012h pir2 092h pie2 112h ? 192h pmadrh 212h ssp1add 292h ccpr1h 312h ? 392h ? 013h ?093h ?113h ? 193h pmdatl 213h ssp1msk 293h ccp1con 313h ? 393h ? 014h ?094h ?114h ? 194h pmdath 214h ssp1stat 294h ? 314h ? 394h iocbp 015h tmr0 095h option_reg 115h ? 195h pmcon1 215h ssp1con1 295h ? 315h ? 395h iocbn 016h tmr1l 096h pcon 116h borcon 196h pmcon2 216h ssp1con2 296h ? 316h ? 396h iocbf 017h tmr1h 097h wdtcon 117h fvrcon 197h vregcon (1) 217h ssp1con3 297h ? 317h ? 397h ? 018h t1con 098h ?118h ?198h ?218h ? 298h ccpr2l 318h ? 398h ? 019h t1gcon 099h osccon 119h ? 199h rcreg 219h ? 299h ccpr2h 319h ? 399h ? 01ah tmr2 09ah oscstat 11ah ? 19ah txreg 21ah ? 29ah ccp2con 31ah ?39ah ? 01bh pr2 09bh adres0l 11bh ? 19bh spbrgl 21bh ?29bh ?31bh ?39bh ? 01ch t2con 09ch adres0h 11ch ? 19ch spbrgh 21ch ? 29ch ? 31ch ? 39ch ? 01dh ? 09dh adcon0 11dh apfcon 19dh rcsta 21dh ? 29dh ? 31dh ? 39dh ? 01eh ? 09eh adcon1 11eh ? 19eh txsta 21eh ?29eh ?31eh ?39eh ? 01fh ?09fh ?11fh ? 19fh baudcon 21fh ?29fh ?31fh ?39fh ? 020h general purpose register 80 bytes 0a0h general purpose register 32 bytes 120h unimplemented read as ? 0 ? 1a0h unimplemented read as ? 0 ? 220h unimplemented read as ? 0 ? 2a0h unimplemented read as ? 0 ? 320h unimplemented read as ? 0 ? 3a0h unimplemented read as ? 0 ? 0bfh 0c0h unimplemented read as ? 0 ? 06fh 0efh 16fh 1efh 26fh 2efh 36fh 3efh 070h common ram 0f0h common ram (accesses 70h ? 7fh) 170h common ram (accesses 70h ? 7fh) 1f0h common ram (accesses 70h ? 7fh) 270h common ram (accesses 70h ? 7fh) 2f0h common ram (accesses 70h ? 7fh) 370h common ram (accesses 70h ? 7fh) 3f0h common ram (accesses 70h ? 7fh) 07fh 0ffh 17fh 1ffh 27fh 2ffh 37fh 3ffh
pic16(l)f1512/3 ds41624b-page 22 preliminary ? 2012 microchip technology inc. table 3-4: pic16(l)f1513 memory map (banks 0-7) legend: = unimplemented data memory locations, read as ? 0 ?. note 1: pic16f1513 only. bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 000h core registers ( ta b l e 3 - 2 ) 080h core registers ( ta b l e 3 - 2 ) 100h core registers ( table 3-2 ) 180h core registers ( table 3-2 ) 200h core registers ( table 3-2 ) 280h core registers ( table 3-2 ) 300h core registers ( table 3-2 ) 380h core registers ( table 3-2 ) 00bh 08bh 10bh 18bh 20bh 28bh 30bh 38bh 00ch porta 08ch trisa 10ch lata 18ch ansela 20ch ? 28ch ? 30ch ? 38ch ? 00dh portb 08dh trisb 10dh latb 18dh anselb 20dh wpub 28dh ? 30dh ? 38dh ? 00eh portc 08eh trisc 10eh latc 18eh anselc 20eh ?28eh ?30eh ?38eh ? 00fh ?08fh ?10fh ?18fh ?20fh ?28fh ?30fh ?38fh ? 010h porte 090h trise 110h ?190h ? 210h wpue 290h ? 310h ? 390h ? 011h pir1 091h pie1 111h ? 191h pmadrl 211h ssp1buf 291h ccpr1l 311h ? 391h ? 012h pir2 092h pie2 112h ? 192h pmadrh 212h ssp1add 292h ccpr1h 312h ? 392h ? 013h ?093h ?113h ? 193h pmdatl 213h ssp1msk 293h ccp1con 313h ? 393h ? 014h ?094h ?114h ? 194h pmdath 214h ssp1stat 294h ? 314h ? 394h iocbp 015h tmr0 095h option_reg 115h ? 195h pmcon1 215h ssp1con1 295h ? 315h ? 395h iocbn 016h tmr1l 096h pcon 116h borcon 196h pmcon2 216h ssp1con2 296h ? 316h ? 396h iocbf 017h tmr1h 097h wdtcon 117h fvrcon 197h vregcon (1) 217h ssp1con3 297h ? 317h ? 397h ? 018h t1con 098h ?118h ?198h ?218h ? 298h ccpr2l 318h ? 398h ? 019h t1gcon 099h osccon 119h ? 199h rcreg 219h ? 299h ccpr2h 319h ? 399h ? 01ah tmr2 09ah oscstat 11ah ? 19ah txreg 21ah ? 29ah ccp2con 31ah ?39ah ? 01bh pr2 09bh adres0l 11bh ? 19bh spbrg 21bh ?29bh ?31bh ?39bh ? 01ch t2con 09ch adres0h 11ch ? 19ch spbrgh 21ch ? 29ch ? 31ch ? 39ch ? 01dh ? 09dh adcon0 11dh apfcon 19dh rcsta 21dh ? 29dh ? 31dh ? 39dh ? 01eh ? 09eh adcon1 11eh ? 19eh txsta 21eh ?29eh ?31eh ?39eh ? 01fh ?09fh ?11fh ? 19fh baudcon 21fh ?29fh ?31fh ?39fh ? 020h general purpose register 80 bytes 0a0h general purpose register 80 bytes 120h general purpose register 80 bytes 1a0h unimplemented read as ? 0 ? 220h unimplemented read as ? 0 ? 2a0h unimplemented read as ? 0 ? 320h unimplemented read as ? 0 ? 3a0h unimplemented read as ? 0 ? 06fh 0efh 16fh 1efh 26fh 2efh 36fh 3efh 070h common ram (accesses 70h ? 7fh) 0f0h common ram (accesses 70h ? 7fh) 170h common ram (accesses 70h ? 7fh) 1f0h common ram (accesses 70h ? 7fh) 270h common ram (accesses 70h ? 7fh) 2f0h common ram (accesses 70h ? 7fh) 370h common ram (accesses 70h ? 7fh) 3f0h common ram (accesses 70h ? 7fh) 07fh 0ffh 17fh 1ffh 27fh 2ffh 37fh 3ffh
? 2012 microchip technology inc. preliminary ds41624b-page 23 pic16(l)f1512/3 table 3-5: pic16(l)f1512/3 memory map (banks 8-30) bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 bank 14 bank 15 400h 40bh core registers ( ta b l e 3 - 2 ) 480h 48bh core registers ( ta b l e 3 - 2 ) 500h 50bh core registers ( ta b l e 3 - 2 ) 580h 58bh core registers ( ta b l e 3 - 2 ) 600h 60bh core registers ( ta b l e 3 - 2 ) 680h 68bh core registers ( ta b l e 3 - 2 ) 700h 70bh core registers ( ta b l e 3 - 2 ) 780h 78bh core registers ( ta b l e 3 - 2 ) 40ch unimplemented read as ? 0 ? 48ch unimplemented read as ? 0 ? 50ch unimplemented read as ? 0 ? 58ch unimplemented read as ? 0 ? 60ch unimplemented read as ? 0 ? 68ch unimplemented read as ? 0 ? 70ch see ta b l e 3 - 6 78ch unimplemented read as ? 0 ? 46fh 4efh 56fh 5efh 66fh 6efh 76fh 7efh 470h common ram (accesses 70h ? 7fh) 4f0h common ram (accesses 70h ? 7fh) 570h common ram (accesses 70h ? 7fh) 5f0h common ram (accesses 70h ? 7fh) 670h common ram (accesses 70h ? 7fh) 6f0h common ram (accesses 70h ? 7fh) 770h common ram (accesses 70h ? 7fh) 7f0h common ram (accesses 70h ? 7fh) 47fh 4ffh 57fh 5ffh 67fh 6ffh 77fh 7ffh bank 16 bank 17 bank 18 bank 19 bank 20 bank 21 bank 22 bank 23 800h 80bh core registers ( ta b l e 3 - 2 ) 880h 88bh core registers ( ta b l e 3 - 2 ) 900h 90bh core registers ( ta b l e 3 - 2 ) 980h 98bh core registers ( ta b l e 3 - 2 ) a00h a0bh core registers ( ta b l e 3 - 2 ) a80h a8bh core registers ( ta b l e 3 - 2 ) b00h b0bh core registers ( ta b l e 3 - 2 ) b80h b8bh core registers ( ta b l e 3 - 2 ) 80ch unimplemented read as ? 0 ? 88ch unimplemented read as ? 0 ? 90ch unimplemented read as ? 0 ? 98ch unimplemented read as ? 0 ? a0ch unimplemented read as ? 0 ? a8ch unimplemented read as ? 0 ? b0ch unimplemented read as ? 0 ? b8ch unimplemented read as ? 0 ? 86fh 8efh 96fh 9efh a6fh aefh b6fh befh 870h common ram (accesses 70h ? 7fh) 8f0h common ram (accesses 70h ? 7fh) 970h common ram (accesses 70h ? 7fh) 9f0h common ram (accesses 70h ? 7fh) a70h common ram (accesses 70h ? 7fh) af0h common ram (accesses 70h ? 7fh) b70h common ram (accesses 70h ? 7fh) bf0h common ram (accesses 70h ? 7fh) 87fh 8ffh 97fh 9ffh a7fh affh b7fh bffh legend: = unimplemented data memory locations, read as ? 0 ?. bank 24 bank 25 bank 26 bank 27 bank 28 bank 29 bank 30 bank 31 c00h c0bh core registers ( ta b l e 3 - 2 ) c80h c8bh core registers ( ta b l e 3 - 2 ) d00h d0bh core registers ( ta b l e 3 - 2 ) d80h d8bh core registers ( ta b l e 3 - 2 ) e00h e0bh core registers ( ta b l e 3 - 2 ) e80h e8bh core registers ( ta b l e 3 - 2 ) f00h f0bh core registers ( ta b l e 3 - 2 ) f80h f8bh core registers ( ta b l e 3 - 2 ) c0ch c6fh unimplemented read as ? 0 ? c8ch cefh unimplemented read as ? 0 ? d0ch d6fh unimplemented read as ? 0 ? d8ch defh unimplemented read as ? 0 ? e0ch e6fh unimplemented read as ? 0 ? e8ch eefh unimplemented read as ? 0 ? f0ch f6fh unimplemented read as ? 0 ? f8ch fefh see ( ta b l e 3 - 7 ) c70h common ram (accesses 70h ? 7fh) cf0h common ram (accesses 70h ? 7fh) d70h common ram (accesses 70h ? 7fh) df0h common ram (accesses 70h ? 7fh) e70h common ram (accesses 70h ? 7fh) ef0h common ram (accesses 70h ? 7fh) f70h common ram (accesses 70h ? 7fh) fe0h common ram (accesses 70h ? 7fh) c7fh cffh d7fh dffh e7fh effh f7fh fefh
pic16(l)f1512/3 ds41624b-page 24 preliminary ? 2012 microchip technology inc. table 3-6: pic16(l)f1512/3 memory map (bank 14) legend: = unimplemented data memory locations, read as ? 0 ?. table 3-7: pic16(l)f1512/3 memory map (bank 31) legend: = unimplemented data memory locations, read as ? 0 ?. bank 14 700h 70bh core registers ( table 3-2 ) 70ch 710h unimplemented read as ? 0 ? 711h aadcon0 712h aadcon1 713h aadcon2 714h aadcon3 715h aadstat 716h aadpre 717h aadacq 718h aadgrd 719h aadcap 71ah aadres0l 71bh aadres0h 71ch aadres1l 71dh aadres1h 71eh ? 71fh ? 720h 76fh unimplemented read as ? 0 ? 770h common ram (accesses 70h ? 7fh) 77fh bank 31 f80h f8bh core registers ( table 3-2 ) f8ch fe3h unimplemented read as ? 0 ? fe4h status_shad fe5h wreg_shad fe6h bsr_shad fe7h pclath_shad fe8h fsr0l_shad fe9h fsr0h_shad feah fsr1l_shad febh fsr1h_shad fech ? fedh stkptr feeh tosl fefh tosh ff0h common ram (accesses 70h ? 7fh) fffh
? 2012 microchip technology inc. preliminary ds41624b-page 25 pic16(l)f1512/3 3.2.6 core function registers summary the core function registers listed in ta b l e 3 - 8 can be addressed from any bank. table 3-8: core function registers summary addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets bank 0-31 x00h or x80h indf0 addressing this location uses contents of fsr0h/fsr0l to address data memory (not a physical register) xxxx xxxx uuuu uuuu x01h or x81h indf1 addressing this location uses contents of fsr1h/fsr1l to address data memory (not a physical register) xxxx xxxx uuuu uuuu x02h or x82h pcl program counter (pc) least significant byte 0000 0000 0000 0000 x03h or x83h status ? ? ?to pd zdcc ---1 1000 ---q quuu x04h or x84h fsr0l indirect data memory address 0 low pointer 0000 0000 uuuu uuuu x05h or x85h fsr0h indirect data memory address 0 high pointer 0000 0000 0000 0000 x06h or x86h fsr1l indirect data memory address 1 low pointer 0000 0000 uuuu uuuu x07h or x87h fsr1h indirect data memory address 1 high pointer 0000 0000 0000 0000 x08h or x88h bsr ? ? ? bsr4 bsr3 bsr2 bsr1 bsr0 ---0 0000 ---0 0000 x09h or x89h wreg working register 0000 0000 uuuu uuuu x0ah or x8ah pclath ? write buffer for the upper 7 bits of the program counter -000 0000 -000 0000 x0bh or x8bh intcon gie peie tmr0ie inte iocie tmr0if intf iocif 0000 0000 0000 0000 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?.
pic16(l)f1512/3 ds41624b-page 26 preliminary ? 2012 microchip technology inc. 3.2.7 special function registers summary the special function registers are listed in ta bl e 3 - 9 . table 3-9: special function register summary addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets bank 0 00ch porta porta data latch when written: porta pins when read xxxx xxxx uuuu uuuu 00dh portb portb data latch when written: portb pins when read xxxx xxxx uuuu uuuu 00eh portc portc data latch when written: portc pins when read xxxx xxxx uuuu uuuu 00fh ? unimplemented ? ? 010h porte ? ? ? ?re3 ? ? ? ---- x--- ---- u--- 011h pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 0000 0000 0000 0000 012h pir2 osfif ? ? ?bclif ? ? ccp2if 0--- 0--0 0--- 0--0 013h ? unimplemented ? ? 014h ? unimplemented ? ? 015h tmr0 timer0 module register xxxx xxxx uuuu uuuu 016h tmr1l holding register for the least significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 017h tmr1h holding register for the most significant byte of the 16-bit tmr1 register xxxx xxxx uuuu uuuu 018h t1con tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ?tmr1on 0000 00-0 uuuu uu-u 019h t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss<1:0> 0000 0x00 uuuu uxuu 01ah tmr2 timer 2 module register 0000 0000 0000 0000 01bh pr2 timer 2 period register 1111 1111 1111 1111 01ch t2con ? t2outps<3:0> tmr2on t2ckps<1:0> -000 0000 -000 0000 01dh ? unimplemented ? ? 01eh ? unimplemented ? ? 01fh ? unimplemented ? ? bank 1 08ch trisa porta data direction register 1111 1111 1111 1111 08dh trisb portb data direction register 1111 1111 1111 1111 08eh trisc portc data direction register 1111 1111 1111 1111 08fh ? unimplemented ? ? 090h trise ? ? ? ? ? (2) ? ? ? ---- 1--- ---- 1--- 091h pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 0000 0000 0000 0000 092h pie2 osfie ? ? ?bclie ? ? ccp2ie 0--- 0--0 0--- 0--0 093h ? unimplemented ? ? 094h ? unimplemented ? ? 095h option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 1111 1111 1111 1111 096h pcon stkovf stkunf ?rwdt rmclr ri por bor 00-1 11qq qq-q qquu 097h wdtcon ? ? wdtps<4:0> swdten --01 0110 --01 0110 098h ? unimplemented ? ? 099h osccon ? ircf<3:0> ?scs<1:0> -011 1-00 -011 1-00 09ah oscstat soscr ?ostshfiofr ? ? lfiofr hfiofs 0-q0 --00 q-qq --0q 09bh adres0l (3) a/d result register low xxxx xxxx uuuu uuuu 09ch adres0h (3) a/d result register high xxxx xxxx uuuu uuuu 09dh adcon0 (3) ?chs<4:0> go/done adon -000 0000 -000 0000 09eh adcon1 (3) adfm adcs<2:0> ? ? adpref<1:0> 0000 --00 0000 --00 09fh ? unimplemented ? ? legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: pic16f1512/3 only. 2: unimplemented, read as ? 1 ?. 3: this register is available in bank 1 and bank 14 under similar register names. see section 16.5.1 ?adc register mapping? .
? 2012 microchip technology inc. preliminary ds41624b-page 27 pic16(l)f1512/3 bank 2 10ch lata porta data latch xxxx xxxx uuuu uuuu 10dh latb portb data latch xxxx xxxx uuuu uuuu 10eh latc portc data latch xxxx xxxx uuuu uuuu 10fh to 115h ? unimplemented ? ? 116h borcon sboren borfs ? ? ? ? ? borrdy 10-- ---q uu-- ---u 117h fvrcon fvren fvrrdy tsen tsrng ? ?adfvr<1:0> 0q00 --00 0q00 --00 118h to 11ch ? unimplemented ? ? 11dh apfcon ? ? ? ? ? ? sssel ccp2sel ---- --00 ---- --00 11eh ? unimplemented ? ? 11fh ? unimplemented ? ? bank 3 18ch ansela ? ?ansa5 ? ansa3 ansa2 ansa1 ansa0 --1- 1111 --1- 1111 18dh anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 --11 1111 --11 1111 18eh anselc ansc7 ansc6 ansc5 ansc4 ansc3 ansc2 ? ? 1111 1100 1111 1100 18fh ? unimplemented ? ? 190h ? unimplemented ? ? 191h pmadrl program memory address register low byte 0000 0000 0000 0000 192h pmadrh ? program memory address register high byte 1000 0000 1000 0000 193h pmdatl program memory data register low byte xxxx xxxx uuuu uuuu 194h pmdath ? ? program memory data register high byte --xx xxxx --uu uuuu 195h pmcon1 ? (2) cfgs lwlo free wrerr wren wr rd 1000 x000 1000 q000 196h pmcon2 program memory control register 2 0000 0000 0000 0000 197h vregcon (1) ? ? ? ? ? ? vregpm reserved ---- --01 ---- --01 198h ? unimplemented ? ? 199h rcreg usart receive data register 0000 0000 0000 0000 19ah txreg usart transmit data register 0000 0000 0000 0000 19bh spbrgl brg<7:0> 0000 0000 0000 0000 19ch spbrgh brg<15:8> 0000 0000 0000 0000 19dh rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19eh txsta csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 19fh baudcon abdovf rcidl ? sckp brg16 ? wue abden 01-0 0-00 01-0 0-00 table 3-9: special function register summary (continued) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: pic16f1512/3 only. 2: unimplemented, read as ? 1 ?. 3: this register is available in bank 1 and bank 14 under similar register names. see section 16.5.1 ?adc register mapping? .
pic16(l)f1512/3 ds41624b-page 28 preliminary ? 2012 microchip technology inc. bank 4 20ch ? unimplemented ? ? 20dh wpub wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 1111 1111 1111 1111 20eh ? unimplemented ? ? 20fh ? unimplemented ? ? 210h wpue ? ? ? ? wpue3 ? ? ? ---- 1--- ---- 1--- 211h ssp1buf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 212h ssp1add synchronous serial port (i 2 c? mode) address register 0000 0000 0000 0000 213h ssp1msk synchronous serial port (i 2 c? mode) address mask register 1111 1111 1111 1111 214h ssp1stat smp cke d/a psr/w ua bf 0000 0000 0000 0000 215h ssp1con1 wcol sspov sspen ckp sspm<3:0> 0000 0000 0000 0000 216h ssp1con2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 217h ssp1con3 acktim pcie scie boen sdaht sbcde ahen dhen 0000 0000 0000 0000 218h to 21fh ? unimplemented ? ? bank 5 28ch to 290h ? unimplemented ? ? 291h ccpr1l capture/compare/pwm register 1 (lsb) xxxx xxxx uuuu uuuu 292h ccpr1h capture/compare/pwm register 1 (msb) xxxx xxxx uuuu uuuu 293h ccp1con ? ? dc1b<1:0> ccp1m<3:0> --00 0000 --00 0000 294h to 297h ? unimplemented ? ? 298h ccpr2l capture/compare/pwm register 2 (lsb) xxxx xxxx uuuu uuuu 299h ccpr2h capture/compare/pwm register 2 (msb) xxxx xxxx uuuu uuuu 29ah ccp2con ? ? dc2b<1:0> ccp2m<3:0> --00 0000 --00 0000 29bh to 29fh ? unimplemented ? ? bank 6 30ch to 31fh ? unimplemented ? ? bank 7 38ch to 393h ? unimplemented ? ? 394h iocbp iocbp<7:0> 0000 0000 0000 0000 395h iocbn iocbn<7:0> 0000 0000 0000 0000 396h iocbf iocbf<7:0> 0000 0000 0000 0000 397h to 39fh ? unimplemented ? ? bank 8-13 x0ch or x8ch to x1fh or x9fh ? unimplemented ? ? table 3-9: special function register summary (continued) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: pic16f1512/3 only. 2: unimplemented, read as ? 1 ?. 3: this register is available in bank 1 and bank 14 under similar register names. see section 16.5.1 ?adc register mapping? .
? 2012 microchip technology inc. preliminary ds41624b-page 29 pic16(l)f1512/3 bank 14 70ch to 710h ? unimplemented ? ? 711h aadcon0 (3) ?chs<4:0> go/done adon -000 0000 -000 0000 712h aadcon1 (3) adfm adcs<2:0> ? ? adpref<1:0> 0000 --00 0000 --00 713h aadcon2 ?trigsel<2:0> ? ? ? ? -000 ---- -000 ---- 714h aadcon3 adeppol adippol adolen adoen adooen ? adipen addsen 0000 0-00 0000 0-00 715h aadstat ? ? ? ? ? adconv adstg<1:0> ---- -000 ---- -000 716h aadpre ? adpre<6:0> -000 0000 -000 0000 717h aadacq ? adacq<6:0> -000 0000 -000 0000 718h aadgrd grdboe grdaoe grdpol ? ? ? ? ? 000- ---- 000- ---- 719h aadcap ? ? ? ? ? addcap<2:0> ---- -000 ---- -000 71ah aadres0l (3) a/d result 0 register low xxxx xxxx uuuu uuuu 71bh aadres0h (3) a/d result 0 register high xxxx xxxx uuuu uuuu 71ch aadres1l a/d result 1 register low xxxx xxxx uuuu uuuu 71dh aadres1h a/d result 1 register high xxxx xxxx uuuu uuuu 71eh ? unimplemented ? ? bank 15-30 x0ch or x8ch to x1fh or x9fh ? unimplemented ? ? bank 31 f8ch to fe3h ? unimplemented ? ? fe4h status_shad ? ? ? ? ?zdcc ---- -xxx ---- -uuu fe5h wreg_shad working register shadow xxxx xxxx uuuu uuuu fe6h bsr_shad ? ? ? bank select register shadow ---x xxxx ---u uuuu fe7h pclath_shad ? program counter latch high register shadow -xxx xxxx uuuu uuuu fe8h fsr0l_shad indirect data memory address 0 low pointer shadow xxxx xxxx uuuu uuuu fe9h fsr0h_shad indirect data memory address 0 high pointer shadow xxxx xxxx uuuu uuuu feah fsr1l_shad indirect data memory address 1 low pointer shadow xxxx xxxx uuuu uuuu febh fsr1h_shad indirect data memory address 1 high pointer shadow xxxx xxxx uuuu uuuu fech ? unimplemented ? ? fedh stkptr ? ? ? current stack pointer ---1 1111 ---1 1111 feeh tosl top of stack low byte xxxx xxxx uuuu uuuu fefh tosh ? top of stack high byte -xxx xxxx -uuu uuuu table 3-9: special function register summary (continued) addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: pic16f1512/3 only. 2: unimplemented, read as ? 1 ?. 3: this register is available in bank 1 and bank 14 under similar register names. see section 16.5.1 ?adc register mapping? .
pic16(l)f1512/3 ds41624b-page 30 preliminary ? 2012 microchip technology inc. 3.3 pcl and pclath the program counter (pc) is 15 bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high byte (pc<14:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 3-4 shows the five situations for the loading of the pc. figure 3-4: loading of pc in different situations 3.3.1 modifying pcl executing any instruction with the pcl register as the destination simultaneously causes the program counter pc<14:8> bits (pch) to be replaced by the contents of the pclath register. this allows the entire contents of the pc to be changed by writing the desired upper seven bits to the pclath register. when the lower eight bits are written to the pcl register, all 15 bits of the pc will change to the values contained in the pclath register and those being written to the pcl register. 3.3.2 computed goto a computed goto is accomplished by adding an offset to the pc ( addwf pcl ). when performing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). refer to the application note an556, ?implementing a table read? (ds00556). 3.3.3 computed function calls a computed function call allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. when performing a table read using a computed function call , care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). if using the call instruction, the pch<2:0> and pcl registers are loaded with the operand of the call instruction. pch<6:3> is loaded with pclath<6:3>. the callw instruction enables computed calls by combining pclath and w to form the destination address. a computed callw is accomplished by loading the w register with the desired address and executing callw . the pcl register is loaded with the value of w and pch is loaded with pclath. 3.3.4 branching the branching instructions add an offset to the pc. this allows relocatable code and code that crosses page boundaries. there are two forms of branching, brw and bra . the pc will have incremented to fetch the next instruction in both cases. when using either branching instruction, a pcl memory boundary may be crossed. if using brw , load the w register with the desired unsigned address and execute brw . the entire pc will be loaded with the address pc + 1 + w. if using bra , the entire pc will be loaded with pc + 1 +, the signed value of the operand of the bra instruction. pcl pch 0 14 pc 0 6 7 alu result 8 pclath pcl pch 0 14 pc 0 6 4 opcode <10:0> 11 pclath pcl pch 0 14 pc 0 6 7 w 8 pclath instruction with pcl as destination goto, call callw pcl pch 0 14 pc pc + w 15 brw pcl pch 0 14 pc pc + opcode <8:0> 15 bra
? 2012 microchip technology inc. preliminary ds41624b-page 31 pic16(l)f1512/3 3.4 stack all devices have a 16-level x 15-bit wide hardware stack (refer to figures 3-5 through 3-8 ). the stack space is not part of either program or data space. the pc is pushed onto the stack when call or callw instructions are executed or an interrupt causes a branch. the stack is poped in the event of a return , retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer if the stvren bit is programmed to ? 0 ? (configuration word 2). this means that after the stack has been pushed sixteen times, the seventeenth push overwrites the value that was stored from the first push. the eighteenth push overwrites the second push (and so on). the stkovf and stkunf flag bits will be set on an overflow/underflow, regardless of whether the reset is enabled. 3.4.1 accessing the stack the stack is available through the tosh, tosl and stkptr registers. stkptr is the current value of the stack pointer. tosh:tosl register pair points to the top of the stack. both registers are read/writable. tos is split into tosh and tosl due to the 15-bit size of the pc. to access the stack, adjust the value of stkptr, which will position tosh:tosl, then read/write to tosh:tosl. stkptr is five bits to allow detection of overflow and underflow. during normal program operation, call, callw and interrupts will increment stkptr while retlw , return , and retfie will decrement stkptr. at any time stkptr can be inspected to see how much stack is left. the stkptr always points at the currently used place on the stack. therefore, a call or callw will increment the stkptr and then write the pc, and a return will unload the pc and then decrement stkptr. reference figure 3-5 through 3-8 for examples of accessing the stack. figure 3-5: accessing the stack example 1 note 1: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, callw , return , retlw and retfie instructions or the vectoring to an interrupt address. note: care should be taken when modifying the stkptr while interrupts are enabled. 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 0x0000 stkptr = 0x1f initial stack configuration: after reset, the stack is empty. the empty stack is initialized so the stack pointer is pointing at 0x1f. if the stack overflow/underflow reset is enabled, the tosh/tosl registers will return ? 0 ?. if the stack overflow/underflow reset is disabled, the tosh/tosl registers will return the contents of stack address 0x0f. 0x1f stkptr = 0x1f stack reset disabled (stvren = 0 ) stack reset enabled (stvren = 1 ) tosh:tosl tosh:tosl
pic16(l)f1512/3 ds41624b-page 32 preliminary ? 2012 microchip technology inc. figure 3-6: accessing the stack example 2 figure 3-7: accessing the stack example 3 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 return address 0x00 stkptr = 0x00 this figure shows the stack configuration after the first call or a single interrupt. if a return instruction is executed, the return addre ss will be placed in the program counter and the stack pointer decremented to the empty state (0x1f). tosh:tosl 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 return address 0x06 return address 0x05 return address 0x04 return address 0x03 return address 0x02 return address 0x01 return address 0x00 stkptr = 0x06 after seven call s or six call s and an interrupt, the stack looks like the figure on the left. a series of return instructions will repeatedly place the return addresses into the program counter and pop the stack. tosh:tosl
? 2012 microchip technology inc. preliminary ds41624b-page 33 pic16(l)f1512/3 figure 3-8: accessing the stack example 4 3.4.2 overflow/ underflow reset if the stvren bit in configuration word 2 is programmed to ? 1 ?, the device will be reset if the stack is pushed beyond the sixteenth level or poped beyond the first level, setting the appropriate bits (stkovf or stkunf, respectively) in the pcon register. 3.5 indirect addressing the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the file select registers (fsr). if the fsrn address specifies one of the two indfn registers, the read will return ? 0 ? and the write will not occur (though status bits may be affected). the fsrn register value is created by the pair fsrnh and fsrnl. the fsr registers form a 16- bit address that allows an addressing space with 65536 locations. these locations are divided into three memory regions: ? traditional data memory ? linear data memory ? program flash memory 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 return address 0x00 stkptr = 0x10 when the stack is full, the next call or an interrupt will set the stack pointer to 0x10. this is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. if the stack overflow/underflow reset is enabled, a reset will occur and location 0x00 will not be overwritten. return address return address return address return address return address return address return address return address return address return address return address return address return address return address return address tosh:tosl
pic16(l)f1512/3 ds41624b-page 34 preliminary ? 2012 microchip technology inc. figure 3-9: indirect addressing 0x0000 0x0fff traditional fsr address range data memory 0x1000 reserved linear data memory reserved 0x2000 0x29af 0x29b0 0x7fff 0x8000 0xffff 0x0000 0x0fff 0x0000 0x7fff program flash memory note: not all memory regions are completely implemented. consult device memory tables for memory limits. 0x1fff
? 2012 microchip technology inc. preliminary ds41624b-page 35 pic16(l)f1512/3 3.5.1 traditional data memory the traditional data memory is a region from fsr address 0x000 to fsr address 0xfff. the addresses correspond to the absolute addresses of all sfr, gpr and common registers. figure 3-10: traditio nal data memory map indirect addressing direct addressing bank select location select 4bsr 6 0 from opcode fsrxl 70 bank select location select 00000 00001 00010 11111 0x00 0x7f bank 0 bank 1 bank 2 bank 31 0 fsrxh 70 0000
pic16(l)f1512/3 ds41624b-page 36 preliminary ? 2012 microchip technology inc. 3.5.2 linear data memory the linear data memory is the region from fsr address 0x2000 to fsr address 0x29af. this region is a virtual region that points back to the 80-byte blocks of gpr memory in all the banks. unimplemented memory reads as 0x00. use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the fsr beyond one bank will go directly to the gpr memory of the next bank. the 16 bytes of common memory are not included in the linear data memory region. figure 3-11: linear data memory map 3.5.3 program flash memory to make constant data access easier, the entire program flash memory is mapped to the upper half of the fsr address space. when the msb of fsrnh is set, the lower 15 bits are the address in program memory which will be accessed through indf. only the lower eight bits of each memory location is accessible via indf. writing to the program flash memory cannot be accomplished via the fsr/indf interface. all instructions that access program flash memory via the fsr/indf interface will require one additional instruction cycle to complete. figure 3-12: program flash memory map 7 0 1 7 0 0 location select 0x2000 fsrnh fsrnl 0x020 bank 0 0x06f 0x0a0 bank 1 0x0ef 0x120 bank 2 0x16f 0xf20 bank 30 0xf6f 0x29af 0 7 1 7 0 0 location select 0x8000 fsrnh fsrnl 0x0000 0x7fff 0xffff program flash memory (low 8 bits)
? 2012 microchip technology inc. preliminary ds41624b-page 37 pic16(l)f1512/3 4.0 device configuration device configuration consists of configuration words, code protection and device id. 4.1 configuration words there are several configuration word bits that allow different oscillator and memory protection options. these are implemented as configuration word 1 at 8007h and configuration word 2 at 8008h. note: the debug bit in configuration word 2 is managed automatically by device development tools including debuggers and programmers. for normal device operation, this bit should be maintained as a ? 1 ?.
pic16(l)f1512/3 ds41624b-page 38 preliminary ? 2012 microchip technology inc. register 4-1: co nfiguration word 1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 u-1 fcmen ieso clkouten boren<1:0> ? bit 13 bit 8 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 cp mclre pwrte wdte<1:0> fosc<2:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?1? ?0? = bit is cleared ?1? = bit is set -n = value when blank or after bulk erase bit 13 fcmen: fail-safe clock monitor enable bit 1 = fail-safe clock monitor is enabled 0 = fail-safe clock monitor is disabled bit 12 ieso: internal external switchover bit 1 = internal/external switchover mode is enabled 0 = internal/external switchover mode is disabled bit 11 clkouten : clock out enable bit if fosc configuration bits are set to lp, xt, hs modes : this bit is ignored, clkout function is disabled. oscillator function on the clkout pin. all other fosc modes : 1 = clkout function is disabled. i/o function on the clkout pin. 0 = clkout function is enabled on the clkout pin bit 10-9 boren<1:0>: brown-out reset enable bits 11 = bor enabled 10 = bor enabled during operation and disabled in sleep 01 = bor controlled by sboren bit of the borcon register 00 = bor disabled bit 8 unimplemented: read as ? 1 ? bit 7 cp : code protection bit 1 = program memory code protection is disabled 0 = program memory code protection is enabled bit 6 mclre: mclr /v pp pin function select bit if lvp bit = 1 : this bit is ignored. if lvp bit = 0 : 1 =mclr /v pp pin function is mclr ; weak pull-up enabled. 0 =mclr /v pp pin function is digital input; mclr internally disabled; weak pull-up under control of wpue3 bit. bit 5 pwrte : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 4-3 wdte<1:0>: watchdog timer enable bit 11 = wdt enabled 10 = wdt enabled while running and disabled in sleep 01 = wdt controlled by the swdten bit in the wdtcon register 00 = wdt disabled
? 2012 microchip technology inc. preliminary ds41624b-page 39 pic16(l)f1512/3 bit 2-0 fosc<2:0>: oscillator selection bits 111 = ech: external clock, high-power mode (4-20 mhz): device clock supplied to clkin pin 110 = ecm: external clock, medium-power mode (0.5-4 mhz): device clock supplied to clkin pin 101 = ecl: external clock, low-power mode (0-0.5 mhz): device clock supplied to clkin pin 100 = intosc oscillator: i/o function on clkin pin 011 = extrc oscillator: external rc circuit connected to clkin pin 010 = hs oscillator: high-speed crystal/resonator connected between osc1 and osc2 pins 001 = xt oscillator: crystal/resonator connected between osc1 and osc2 pins 000 = lp oscillator: low-power crystal connected between osc1 and osc2 pins register 4-1: configurat ion word 1 (continued)
pic16(l)f1512/3 ds41624b-page 40 preliminary ? 2012 microchip technology inc. register 4-2: co nfiguration word 2 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 u-1 lvp debug lpbor borv stvren ? bit 13 bit 8 u-1 u-1 u-1 r/p-1 u-1 u-1 r/p-1 r/p-1 ? ? ? vcapen (1) ? ?wrt<1:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?1? ?0? = bit is cleared ?1? = bit is set -n = value when blank or after bulk erase bit 13 lvp: low-voltage programming enable bit 1 = low-voltage programming enabled 0 = high-voltage on mclr must be used for programming bit 12 debug : in-circuit debugger mode bit 1 = in-circuit debugger disabled, icspclk and icspdat are general purpose i/o pins 0 = in-circuit debugger enabled, icspclk and icspdat are dedicated to the debugger bit 11 lpbor : low-power bor bit 1 = low-power bor is disabled 0 = low-power bor is enabled bit 10 borv: brown-out reset voltage selection bit 1 = brown-out reset voltage set to 1.9v (typical) for pic16lf1512/3 and 2.45v on pic16f1512/3 0 = brown-out reset voltage set to 2.7v (typical) bit 9 stvren: stack overflow/underflow reset enable bit 1 = stack overflow or underflow will cause a reset 0 = stack overflow or underflow will not cause a reset bit 8-5 unimplemented: read as ? 1 ? bit 4 vcapen : voltage regulator capacitor enable bits (1) if pic16lf1512/3 ( regulator disabled) : these bits are ignored. all v cap pin functions are disabled. if pic16f1512/3 ( regulator enabled) : 0 =v cap functionality is enabled on ra5 1 =all v cap pin functions are disabled bit 3-2 unimplemented: read as ? 1 ? bit 1-0 wrt<1:0>: flash memory self-write protection bits 2 kw flash memory (pic16(l)f1512 only) : 11 = write protection off 10 = 000h to 1ffh write-protected, 200h to 7ffh may be modified by pmcon control 01 = 000h to 3ffh write-protected, 400h to 7ffh may be modified by pmcon control 00 = 000h to 7ffh write-protected, no addresses may be modified by pmcon control 4 kw flash memory (pic16(l)f1513 only) : 11 = write protection off 10 = 000h to 1ffh write-protected, 200h to fffh may be modified by pmcon control 01 = 000h to 7ffh write-protected, 800h to fffh may be modified by pmcon control 00 = 000h to fffh write-protected, no addresses may be modified by pmcon control note 1: pic16f1512/3 only.
? 2012 microchip technology inc. preliminary ds41624b-page 41 pic16(l)f1512/3 4.2 code protection code protection allows the device to be protected from unauthorized access. program memory protection is controlled independently. internal access to the program memory is unaffected by any code protection setting. 4.2.1 program memory protection the entire program memory space is protected from external reads and writes by the cp bit in configuration words. when cp = 0 , external reads and writes of program memory are inhibited and a read will return all ? 0 ?s. the cpu can continue to read program memory, regardless of the protection bit settings. writing the program memory is dependent upon the write protection setting. see section 4.3 ?write protection? for more information. 4.3 write protection write protection allows the device to be protected from unintended self-writes. applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. the wrt<1:0> bits in configuration words define the size of the program memory block that is protected. 4.4 user id four memory locations (8000h-8003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are readable and writable during normal execution. see section 11.4 ?user id, device id and configuration word access? for more information on accessing these memory locations. for more information on checksum calculation, see the ? pic16(l)f151x/152x memory programming specification ? (ds41442).
pic16(l)f1512/3 ds41624b-page 42 preliminary ? 2012 microchip technology inc. 4.5 device id and revision id the memory location 8006h is where the device id and revision id are stored. the upper nine bits hold the device id. the lower five bits hold the revision id. see section 11.4 ?user id, device id and configuration word access? for more information on accessing these memory locations. development tools, such as device programmers and debuggers, may be used to read the device id and revision id. register 4-3: deviceid: device id register rrrrrr dev<8:3> bit 13 bit 8 rrrrrrrr dev<2:0> rev<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?1? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared p = programmable bit bit 13-5 dev<8:0>: device id bits bit 4-0 rev<4:0>: revision id bits these bits are used to identify the revision (see table under dev<8:0> above). device deviceid<13:0> values dev<8:0> rev<4:0> pic16f1512 01 0111 000 x xxxx pic16f1513 01 0110 010 x xxxx pic16lf1512 01 0111 001 x xxxx pic16lf1513 01 0111 010 x xxxx
? 2012 microchip technology inc. preliminary ds41624b-page 43 pic16(l)f1512/3 5.0 oscillator module (with fail-safe clock monitor) 5.1 overview the oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing performance and minimizing power consumption. figure 5-1 illustrates a block diagram of the oscillator module. clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and resistor-capacitor (rc) circuits. in addition, the system clock source can be supplied from one of two internal oscillators, with a choice of speeds selectable via software. additional clock features include: ? selectable system clock source between external or internal sources via software. ? two-speed start-up mode, which minimizes latency between external oscillator start-up and code execution. ? fail-safe clock monitor (fscm) designed to detect a failure of the external clock source (lp, xt, hs, ec or rc modes) and switch automatically to the internal oscillator. ? oscillator start-up timer (ost) ensures stability of crystal oscillator sources ? fast start-up oscillator allows internal circuits to power up and stabilize before switching to the 16 mhz hfintosc the oscillator module can be configured in one of eight clock modes. 1. ecl ? external clock low-power mode (0 mhz to 0.5 mhz) 2. ecm ? external clock medium-power mode (0.5 mhz to 4 mhz) 3. ech ? external clock high-power mode (4 mhz to 20 mhz) 4. lp ? 32 khz low-power crystal mode. 5. xt ? medium gain crystal or ceramic resonator oscillator mode (up to 4 mhz) 6. hs ? high gain crystal or ceramic resonator mode (4 mhz to 20 mhz) 7. rc ? external resistor-capacitor (rc). 8. intosc ? internal oscillator (31 khz to 16 mhz). clock source modes are selected by the fosc<2:0> bits in the configuration words. the fosc bits determine the type of oscillator that will be used when the device is first powered. the ec clock mode relies on an external logic level signal as the device clock source. the lp, xt and hs clock modes require an external crystal or resonator to be connected to the device. each mode is optimized for a different frequency range. the rc clock mode requires an external resistor and capacitor to set the oscillator frequency. the intosc internal oscillator block produces a low and high frequency clock source, designated lfintosc and hfintosc. (see internal oscillator block, figure 5-1 ). a wide selection of device clock frequencies may be derived from these two clock sources.
pic16(l)f1512/3 ds41624b-page 44 preliminary ? 2012 microchip technology inc. figure 5-1: simplified pic ? mcu clock source block diagram osc2 osc1 primary oscillator (osc) sosco/ t1cki sosci secondary oscillator (sosc) 16 mhz primary osc start-up osc lf-intosc (31.25 khz) intosc divide circuit ircf<3:0> intosc primary clock secondary clock clock switch mux 01 00 1x low-power mode event switch (scs<1:0>) 2 4 secondary oscillator primary oscillator internal oscillator hf-16 mhz hf-4 mhz hf-2 mhz hf-1 mhz hf-500 khz hf-250 khz hf-125 khz hf-62.5 khz hf-31.25 khz lf-31 khz hf-8 mhz internal oscillator mux 4 1111 1110 1101 1100 1011 1010/ 0111 1001/ 0110 1000/ 0101 0100 0011 0010 0001 0000 /1 /2 /4 /8 /16 /32 /64 /128 /256 /512 start-up control logic
? 2012 microchip technology inc. preliminary ds41624b-page 45 pic16(l)f1512/3 5.2 clock source types clock sources can be classified as external or internal. external clock sources rely on external circuitry for the clock source to function. examples are: oscillator modules (ec mode), quartz crystal resonators or ceramic resonators (lp, xt and hs modes) and resistor-capacitor (rc) mode circuits. internal clock sources are contained within the oscillator module. the internal oscillator block has two internal oscillators that are used to generate the internal system clock sources: the 16 mhz high-frequency internal oscillator and the 31 khz low-frequency internal oscillator (lfintosc). the system clock can be selected between external or internal clock sources via the system clock select (scs) bits in the osccon register. see section 5.3 ?clock switching? for additional information. 5.2.1 external clock sources an external clock source can be used as the device system clock by performing one of the following actions: ? program the fosc<2:0> bits in the configuration words to select an external clock source that will be used as the default system clock upon a device reset. ? write the scs<1:0> bits in the osccon register to switch the system clock source to: - secondary oscillator during run-time, or - an external clock source determined by the value of the fosc bits. see section 5.3 ?clock switching? for more informa- tion. 5.2.1.1 ec mode the external clock (ec) mode allows an externally generated logic level signal to be the system clock source. when operating in this mode, an external clock source is connected to the osc1 input. osc2/clkout is available for general purpose i/o or clkout. figure 5-2 shows the pin connections for ec mode. ec mode has three power modes to select from through configuration words: ? high power, 4-20 mhz (fosc = 111 ) ? medium power, 0.5-4 mhz (fosc = 110 ) ? low power, 0-0.5 mhz (fosc = 101 ) the oscillator start-up timer (ost) is disabled when ec mode is selected. therefore, there is no delay in operation after a power-on reset (por) or wake-up from sleep. because the pic ? mcu design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. upon restarting the external clock, the device will resume operation as if no time had elapsed. figure 5-2: external clock (ec) mode operation 5.2.1.2 lp, xt, hs modes the lp, xt and hs modes support the use of quartz crystal resonators or ceramic resonators connected to osc1 and osc2 ( figure 5-3 ). the three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. lp oscillator mode selects the lowest gain setting of the internal inverter-amplifier. lp mode current consumption is the least of the three modes. this mode is designed to drive only 32.768 khz tuning-fork type crystals (watch crystals). xt oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. xt mode current consumption is the medium of the three modes. this mode is best suited to drive resonators with a medium drive level specification. hs oscillator mode selects the highest gain setting of the internal inverter-amplifier. hs mode current consumption is the highest of the three modes. this mode is best suited for resonators that require a high drive setting. figure 5-3 and figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively. osc1/clkin osc2/clkout clock from ext. system pic ? mcu f osc /4 or i/o (1) note 1: output depends upon the clkouten bit of the configuration words.
pic16(l)f1512/3 ds41624b-page 46 preliminary ? 2012 microchip technology inc. figure 5-3: quartz crystal operation (lp, xt or hs mode) figure 5-4: ceramic resonator operation (xt or hs mode) 5.2.1.3 oscillator start-up timer (ost) if the oscillator module is configured for lp, xt or hs modes, the oscillator start-up timer (ost) counts 1024 oscillations from osc1. this occurs following a power-on reset (por) and when the power-up timer (pwrt) has expired (if configured), or a wake-up from sleep. during this time, the program counter does not increment and program execution is suspended unless either fscm or two-speed start-up are enabled, in which case code will continue to execute while the ost is counting. the ost ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. in order to minimize latency between external oscillator start-up and code execution, the two-speed clock start-up mode can be selected (see section 5.4 ?two-speed clock start-up mode? ). note 1: quartz crystal characteristics vary according to type, package and manufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. 3: for oscillator design assistance, reference the following microchip applications notes: ? an826, ? crystal oscillator basics and crystal selection for rfpic ? and pic ? devices ? (ds00826) ? an849, ? basic pic ? oscillator design ? (ds00849) ? an943, ? practical pic ? oscillator analysis and design ? (ds00943) ? an949, ? making your oscillator work ? (ds00949) note 1: a series resistor (r s ) may be required for quartz crystals with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m ? to 10 m ?? . c1 c2 quartz r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu crystal osc2/clkout note 1: a series resistor (r s ) may be required for ceramic resonators with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m ? to 10 m ?? . 3: an additional parallel feedback resistor (r p ) may be required for proper ceramic resonator operation. c1 c2 ceramic r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu r p (3) resonator osc2/clkout
? 2012 microchip technology inc. preliminary ds41624b-page 47 pic16(l)f1512/3 5.2.1.4 secondary oscillator the secondary oscillator is a separate crystal oscillator that is associated with the timer1 peripheral. it is optimized for timekeeping operations with a 32.768 khz crystal connected between the sosco and sosci device pins. the secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. refer to section 5.3 ?clock switching? for more information. figure 5-5: quartz crystal operation (secondary oscillator) 5.2.1.5 external rc mode the external resistor-capacitor (rc) modes support the use of an external rc circuit. this allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. the rc circuit connects to osc1. osc2/clkout is available for general purpose i/o or clkout. the function of the osc2/clkout pin is determined by the clkouten bit in configuration words. figure 5-6 shows the external rc mode connections. figure 5-6: external rc modes the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values and the operating temperature. other factors affecting the oscillator frequency are: ? threshold voltage variation ? component tolerances ? packaging variations in capacitance the user also needs to take into account variation due to tolerance of the external rc components used. note 1: quartz crystal characteristics vary according to type, package and manufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. 3: for oscillator design assistance, reference the following microchip applications notes: ? an826, ? crystal oscillator basics and crystal selection for rfpic ? and pic ? devices ? (ds00826) ? an849, ? basic pic ? oscillator design ? (ds00849) ? an943, ? practical pic ? oscillator analysis and design ? (ds00943) ? an949, ? making your oscillator work ? (ds00949) ? tb097, ? interfacing a micro crystal ms1v-t1k 32.768 khz tuning fork crystal to a pic16f690/ss ? (ds91097) ? an1288, ? design practices for low-power external oscillators ? (ds01288) c1 c2 32.768 khz sosci to internal logic pic ? mcu crystal sosco quartz osc2/clkout c ext r ext pic ? mcu osc1/clkin f osc /4 or internal clock v dd v ss recommended values: 10 k ? ? r ext ? 100 k ? , <3v 3 k ? ? r ext ? 100 k ? , 3-5v c ext > 20 pf, 2-5v note 1: output depends upon the clkouten bit of the configuration words. i/o (1)
pic16(l)f1512/3 ds41624b-page 48 preliminary ? 2012 microchip technology inc. 5.2.2 internal clock sources the device may be configured to use the internal oscillator block as the system clock by performing one of the following actions: ? program the fosc<2:0> bits in configuration words to select the intosc clock source, which will be used as the default system clock upon a device reset. ? write the scs<1:0> bits in the osccon register to switch the system clock source to the internal oscillator during run-time. see section 5.3 ?clock switching? for more information. in intosc mode, osc1/clkin is available for general purpose i/o. osc2/clkout is available for general purpose i/o or clkout. the function of the osc2/clkout pin is determined by the clkouten bit in configuration words. the internal oscillator block has two independent oscillators that provides the internal system clock source. 1. the hfintosc (high-frequency internal oscillator) is factory calibrated and operates at 16 mhz. 2. the lfintosc (low-frequency internal oscillator) is uncalibrated and operates at 31 khz. 5.2.2.1 hfintosc the high-frequency internal oscillator (hfintosc) is a factory calibrated 16 mhz internal clock source. the output of the hfintosc connects to a postscaler and multiplexer (see figure 5-1 ). the frequency derived from the hfintosc can be selected via software using the ircf<3:0> bits of the osccon register. see section 5.2.2.4 ?internal oscillator clock switch timing? for more information. the hfintosc is enabled by: ? configure the ircf<3:0> bits of the osccon register for the desired hf frequency, and ?fosc<2:0> = 100 , or ? set the system clock source (scs) bits of the osccon register to ? 1x ?. a fast start-up oscillator allows internal circuits to power up and stabilize before switching to hfintosc. the high-frequency internal oscillator ready bit (hfiofr) of the oscstat register indicates when the hfintosc is running. the high-frequency internal oscillator stable bit (hfiofs) of the oscstat register indicates when the hfintosc is running within 0.5% of its final value. 5.2.2.2 lfintosc the low-frequency internal oscillator (lfintosc) is an uncalibrated 31 khz internal clock source. the output of the lfintosc connects to a postscaler and multiplexer (see figure 5-1 ). select 31 khz, via software, using the ircf<3:0> bits of the osccon register. see section 5.2.2.4 ?internal oscillator clock switch timing? for more information. the lfintosc is also the frequency for the power-up timer (pwrt), watchdog timer (wdt) and fail-safe clock monitor (fscm). the lfintosc is enabled by selecting 31 khz (ircf<3:0> bits of the osccon register = 000) as the system clock source (scs bits of the osccon register = 1x ), or when any of the following are enabled: ? configure the ircf<3:0> bits of the osccon register for the desired lf frequency, and ?fosc<2:0> = 100 , or ? set the system clock source (scs) bits of the osccon register to ? 1x ? peripherals that use the lfintosc are: ? power-up timer (pwrt) ? watchdog timer (wdt) ? fail-safe clock monitor (fscm) the low-frequency internal oscillator ready bit (lfiofr) of the oscstat register indicates when the lfintosc is running.
? 2012 microchip technology inc. preliminary ds41624b-page 49 pic16(l)f1512/3 5.2.2.3 internal oscillator frequency selection the system clock speed can be selected via software using the internal oscillator frequency select bits ircf<3:0> of the osccon register. the output of the 16 mhz hfintosc and 31 khz lfintosc connects to a postscaler and multiplexer (see figure 5-1 ). the internal oscillator frequency select bits ircf<3:0> of the osccon register select the frequency output of the internal oscillators. one of the following frequencies can be selected via software: ?hfintosc -16 mhz -8 mhz -4 mhz -2 mhz -1 mhz - 500 khz (default after reset) - 250 khz - 125 khz - 62.5 khz - 31.25 khz ?lfintosc ?31 khz the ircf<3:0> bits of the osccon register allow duplicate selections for some frequencies. these duplicate choices can offer system design trade-offs. lower power consumption can be obtained when changing oscillator sources for a given frequency. faster transition times can be obtained between frequency changes that use the same oscillator source. 5.2.2.4 internal oscillator clock switch timing when switching between the hfintosc and the lfintosc, the new oscillator may already be shut down to save power (see figure 5-7 ). if this is the case, there is a delay after the ircf<3:0> bits of the osccon register are modified before the frequency selection takes place. the oscstat register will reflect the current active status of the hfintosc and lfintosc oscillators. the sequence of a frequency selection is as follows: 1. ircf<3:0> bits of the osccon register are modified. 2. if the new clock is shut down, a clock start-up delay is started. 3. clock switch circuitry waits for a falling edge of the current clock. 4. the current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. 5. the new clock is now active. 6. the oscstat register is updated as required. 7. clock switch is complete. see figure 5-7 for more details. if the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. clock switching time delays are shown in table 5-1 . start-up delay specifications are located in the oscillator tables of section 25.0 ?electrical specifications? note: following any reset, the ircf<3:0> bits of the osccon register are set to ? 0111 ? and the frequency selection is set to 500 khz. the user can modify the ircf bits to select a different frequency.
pic16(l)f1512/3 ds41624b-page 50 preliminary ? 2012 microchip technology inc. figure 5-7: internal oscillator switch timing hfintosc lfintosc ircf <3:0> system clock hfintosc lfintosc ircf <3:0> system clock ?? 0 ?? 0 ?? 0 ?? 0 start-up time 2-cycle sync running 2-cycle sync running hfintosc lfintosc (fscm and wdt disabled) hfintosc lfintosc (either fscm or wdt enabled) lfintosc hfintosc ircf <3:0> system clock = 0 ? 0 start-up time 2-cycle sync running lfintosc hfintosc lfintosc turns off unless wdt or fscm is enabled
? 2012 microchip technology inc. preliminary ds41624b-page 51 pic16(l)f1512/3 5.3 clock switching the system clock source can be switched between external and internal clock sources via software using the system clock select (scs) bits of the osccon register. the following clock sources can be selected using the scs bits: ? default system oscillator determined by fosc bits in configuration words ? secondary oscillator 32 khz crystal ? internal oscillator block (intosc) 5.3.1 system clock select (scs) bits the system clock select (scs) bits of the osccon register selects the system clock source that is used for the cpu and peripherals. ? when the scs bits of the osccon register = 00 , the system clock source is determined by value of the fosc<2:0> bits in the configuration words. ? when the scs bits of the osccon register = 01 , the system clock source is the secondary oscillator. ? when the scs bits of the osccon register = 1x , the system clock source is chosen by the internal oscillator frequency selected by the ircf<3:0> bits of the osccon register. after a reset, the scs bits of the osccon register are always cleared. when switching between clock sources, a delay is required to allow the new clock to stabilize. these oscillator delays are shown in table 5-1 . 5.3.2 oscillator start-up timer status (osts) bit the oscillator start-up timer status (osts) bit of the oscstat register indicates whether the system clock is running from the external clock source, as defined by the fosc<2:0> bits in the configuration words, or from the internal clock source. in particular, osts indicates that the oscillator start-up timer (ost) has timed out for lp, xt or hs modes. the ost does not reflect the status of the secondary oscillator. 5.3.3 secondary oscillator the secondary oscillator is a separate crystal oscillator associated with the timer1 peripheral. it is optimized for timekeeping operations with a 32.768 khz crystal connected between the sosco and sosci device pins. the secondary oscillator is enabled using the t1oscen control bit in the t1con register. see section 18.0 ?timer1 module with gate control? for more information about the timer1 peripheral. 5.3.4 secondary oscillator ready (soscr) bit the user must ensure that the secondary oscillator is ready to be used before it is selected as a system clock source. the secondary oscillator ready (soscr) bit of the oscstat register indicates whether the secondary oscillator is ready to be used. after the soscr bit is set, the scs bits can be configured to select the secondary oscillator. note: any automatic clock switch, which may occur from two-speed start-up or fail-safe clock monitor, does not update the scs bits of the osccon register. the user can monitor the osts bit of the oscstat register to determine the current system clock source.
pic16(l)f1512/3 ds41624b-page 52 preliminary ? 2012 microchip technology inc. 5.4 two-speed clock start-up mode two-speed start-up mode provides additional power savings by minimizing the latency between external oscillator start-up and code execution. in applications that make heavy use of the sleep mode, two-speed start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power consumption of the device. this mode allows the application to wake-up from sleep, perform a few instructions using the intosc internal oscillator block as the clock source and go back to sleep without waiting for the external oscillator to become stable. two-speed start-up provides benefits when the oscillator module is configured for lp, xt or hs modes. the oscillator start-up timer (ost) is enabled for these modes and must count 1024 oscillations before the oscillator can be used as the system clock source. if the oscillator module is configured for any mode other than lp, xt or hs mode, then two-speed start-up is disabled. this is because the external clock oscillator does not require any stabilization time after por or an exit from sleep. if the ost count reaches 1024 before the device enters sleep mode, the osts bit of the oscstat register is set and program execution switches to the external oscillator. however, the system may never operate from the external oscillator if the time spent awake is very short. 5.4.1 two-speed start-up mode configuration two-speed start-up mode is configured by the following settings: ? ieso (of the configuration words) = 1 ; internal/external switchover bit (two-speed start-up mode enabled). ? scs (of the osccon register) = 00 . ? fosc<2:0> bits in the configuration words configured for lp, xt or hs mode. two-speed start-up mode is entered after: ? power-on reset (por) and, if enabled, after power-up timer (pwrt) has expired, or ? wake-up from sleep. table 5-1: oscillator switching delays note: executing a sleep instruction will abort the oscillator start-up time and will cause the osts bit of the oscstat register to remain clear. note: if fscm is enabled, two-speed start-up will automatically be enabled. switch from switch to frequency oscillator delay sleep/por lfintosc hfintosc 31 khz 31.25khz-16mhz oscillator warm-up delay (t warm ) sleep/por ec, rc dc ? 20 mhz 2 cycles lfintosc ec, rc dc ? 20 mhz 1 cycle of each sleep/por secondary oscillator, lp, xt, hs 32 khz-20 mhz 1024 clock cycles (ost) any clock source hfintosc 31.25 khz-16 mhz 2 ? s (approx.) any clock source lfintosc 31 khz 1 cycle of each any clock source secondary oscillator 32 khz 1024 clock cycles (ost)
? 2012 microchip technology inc. preliminary ds41624b-page 53 pic16(l)f1512/3 5.4.2 two-speed start-up sequence 1. wake-up from power-on reset or sleep. 2. instructions begin execution by the internal oscillator at the frequency set in the ircf<3:0> bits of the osccon register. 3. ost enabled to count 1024 clock cycles. 4. ost timed out, wait for falling edge of the internal oscillator. 5. osts is set. 6. system clock held low until the next falling edge of new clock (lp, xt or hs mode). 7. system clock is switched to external clock source. 5.4.3 checking two-speed clock status checking the state of the osts bit of the oscstat register will confirm if the microcontroller is running from the external clock source, as defined by the fosc<2:0> bits in the configuration words, or the internal oscillator. figure 5-8: two-speed start-up 0 1 1022 1023 pc + 1 t ost t intosc osc1 osc2 program counter system clock pc - n pc
pic16(l)f1512/3 ds41624b-page 54 preliminary ? 2012 microchip technology inc. 5.5 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the device to continue operating should the external oscillator fail. the fscm can detect oscillator failure any time after the oscillator start-up timer (ost) has expired. the fscm is enabled by setting the fcmen bit in the configuration words. the fscm is applicable to all external oscillator modes (lp, xt, hs, ec, rc and secondary oscillator). figure 5-9: fscm block diagram 5.5.1 fail-safe detection the fscm module detects a failed oscillator by comparing the external oscillator to the fscm sample clock. the sample clock is generated by dividing the lfintosc by 64. see figure 5-9 . inside the fail detector block is a latch. the external clock sets the latch on each falling edge of the external clock. the sample clock clears the latch on each rising edge of the sample clock. a failure is detected when an entire half-cycle of the sample clock elapses before the external clock goes low. 5.5.2 fail-safe operation when the external clock fails, the fscm switches the device clock to an internal clock source and sets the bit flag osfif of the pir2 register. setting this flag will generate an interrupt if the osfie bit of the pie2 register is also set. the device firmware can then take steps to mitigate the problems that may arise from a failed clock. the system clock will continue to be sourced from the internal clock source until the device firmware successfully restarts the external oscillator and switches back to external operation. the internal clock source chosen by the fscm is determined by the ircf<3:0> bits of the osccon register. this allows the internal oscillator to be configured before a failure occurs. 5.5.3 fail-safe condition clearing the fail-safe condition is cleared after a reset or changing the scs bits of the osccon register. when the scs bits are changed, the ost is restarted. while the ost is running, the device continues to operate from the intosc selected in osccon. when the ost times out, the fail-safe condition is cleared and the device will be operating from the external clock source. the fail-safe condition must be cleared before the osfif flag can be cleared. 5.5.4 reset or wake-up from sleep the fscm is designed to detect an oscillator failure after the oscillator start-up timer (ost) has expired. the ost is used after waking up from sleep and after any type of reset. the ost is not used with the ec or rc clock modes so that the fscm will be active as soon as the reset or wake-up has completed. when the fscm is enabled, the two-speed start-up is also enabled. therefore, the device will always be executing code while the ost is operating. external lfintosc 64 s r q 31 khz (~32 ? s) 488 hz (~2 ms) clock monitor latch clock failure detected oscillator clock q sample clock note: due to the wide range of oscillator start-up times, the fail-safe circuit is not active during oscillator start-up (i.e., after exiting reset or sleep). after an appropriate amount of time, the user should check the status bits in the oscstat register to verify the oscillator start-up and that the system clock switchover has successfully completed.
? 2012 microchip technology inc. preliminary ds41624b-page 55 pic16(l)f1512/3 figure 5-10: fscm timing diagram oscfif system clock output sample clock failure detected oscillator failure note: the system clock is normally at a much higher frequency than the sample clock. the relative frequencies in this example have been chosen for clarity. (q) te s t test test clock monitor output
pic16(l)f1512/3 ds41624b-page 56 preliminary ? 2012 microchip technology inc. 5.6 oscillator control registers register 5-1: osccon: os cillator control register u-0 r/w-0/0 r/w-1/1 r/w-1/1 r/w-1/1 u-0 r/w-0/0 r/w-0/0 ? ircf<3:0> ? scs<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-3 ircf<3:0>: internal oscillator frequency select bits 1111 =16mhz 1110 =8mhz 1101 =4mhz 1100 =2mhz 1011 =1mhz 1010 = 500 khz (1) 1001 = 250 khz (1) 1000 = 125 khz (1) 0111 = 500 khz (default upon reset) 0110 = 250 khz 0101 = 125 khz 0100 = 62.5 khz 001x = 31.25 khz 000x =31khz lf bit 2 unimplemented: read as ? 0 ? bit 1-0 scs<1:0>: system clock select bits 1x = internal oscillator block 01 = secondary oscillator 00 = clock determined by fosc<2:0> in configuration words. note 1: duplicate frequency derived from hfintosc.
? 2012 microchip technology inc. preliminary ds41624b-page 57 pic16(l)f1512/3 table 5-2: summary of registers asso ciated with clock sources table 5-3: summary of configuration word wi th clock sources register 5-2: oscstat: oscillator status register r-1/q u-0 r-q/q r-0/q u-0 u-0 r-0/0 r-0/q soscr ? osts hfiofr ? ? lfiofr hfiofs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = conditional bit 7 soscr: secondary oscillator ready bit if t1oscen = 1 : 1 = secondary oscillator is ready 0 = secondary oscillator is not ready if t1oscen = 0 : 1 = timer1 clock source is always ready bit 6 unimplemented: read as ? 0 ? bit 5 osts: oscillator start-up timer status bit 1 = running from the clock defined by the fosc<2:0> bits of the configuration words 0 = running from an internal oscillator (fosc<2:0> = 100 ) bit 4 hfiofr: high-frequency internal oscillator ready bit 1 = hfintosc is ready 0 = hfintosc is not ready bit 3-2 unimplemented: read as ? 0 ? bit 1 lfiofr: low-frequency internal oscillator ready bit 1 = lfintosc is ready 0 = lfintosc is not ready bit 0 hfiofs: high-frequency internal oscillator stable bit 1 = hfintosc 16 mhz oscillator is stable and is driving the intosc 0 = hfintosc 16 mhz is not stable, the start-up oscillator is driving intosc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page osccon ? ircf<3:0> ?scs<1:0> 56 oscstat soscr ? osts hfiofr ? ? lfiofr hfiofs 57 pie2 osfie ? ? ? bclie ? ? ccp2ie 74 pir2 osfif ? ? ? bclif ? ? ccp2if 76 t1con tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ? tmr1on 175 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by clock sources. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? fcmen ieso clkouten boren<1:0> ? 38 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by clock sources.
pic16(l)f1512/3 ds41624b-page 58 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds41624b-page 59 pic16(l)f1512/3 6.0 resets there are multiple ways to reset this device: ? power-on reset (por) ? brown-out reset (bor) ? low-power brown-out reset (lpbor) ?mclr reset ?wdt reset ? reset instruction ? stack overflow ? stack underflow ? programming mode exit to a l l o w v dd to stabilize, an optional power-up timer can be enabled to extend the reset time after a bor or por event. a simplified block diagram of the on-chip reset circuit is shown in figure 6-1 . figure 6-1: simplified block di agram of on-chip reset circuit note 1: see table 6-1 for bor active conditions. device reset power-on reset wdt time-out brown-out reset lpbor reset reset instruction mclre sleep bor active (1) pwrt r done pwrte lfintosc v dd icsp? programming mode exit stack pointer
pic16(l)f1512/3 ds41624b-page 60 preliminary ? 2012 microchip technology inc. 6.1 power-on reset (por) the por circuit holds the device in reset until v dd has reached an acceptable level for minimum operation. slow rising v dd , fast operating speeds or analog performance may require greater than minimum v dd . the pwrt, bor or mclr features can be used to extend the start-up period until all device operation conditions have been met. 6.1.1 power-up timer (pwrt) the power-up timer provides a nominal 64 ms time- out on por or brown-out reset. the device is held in reset as long as pwrt is active. the pwrt delay allows additional time for the v dd to rise to an acceptable level. the power-up timer is enabled by clearing the pwrte bit in configuration words. the power-up timer starts after the release of the por and bor. for additional information, refer to application note an607, ?power-up trouble shooting? (ds00607). 6.2 brown-out reset (bor) the bor circuit holds the device in reset when v dd reaches a selectable minimum level. between the por and bor, complete voltage range coverage for execution protection can be implemented. the brown-out reset module has four operating modes controlled by the boren<1:0> bits in configuration words. the four operating modes are: ? bor is always on ? bor is off when in sleep ? bor is controlled by software ? bor is always off refer to tab le 6 - 1 for more information. the brown-out reset voltage level is selectable by configuring the borv bit in configuration words. a v dd noise rejection filter prevents the bor from triggering on small events. if v dd falls below v bor for a duration greater than parameter t bordc , the device will reset. see figure 6-2 for more information. table 6-1: bor operating modes 6.2.1 bor is always on when the boren bits of configuration words are programmed to ? 11 ?, the bor is always on. the device start-up will be delayed until the bor is ready and v dd is higher than the bor threshold. bor protection is active during sleep. the bor does not delay wake-up from sleep. 6.2.2 bor is off in sleep when the boren bits of configuration words are programmed to ? 10 ?, the bor is on, except in sleep. the device start-up will be delayed until the bor is ready and v dd is higher than the bor threshold. bor protection is not active during sleep. the device wake-up will be delayed until the bor is ready. 6.2.3 bor controlled by software when the boren bits of configuration words are programmed to ? 01 ?, the bor is controlled by the sboren bit of the borcon register. the device start- up is not delayed by the bor ready condition or the v dd level. bor protection begins as soon as the bor circuit is ready. the status of the bor circuit is reflected in the borrdy bit of the borcon register. bor protection is unchanged by sleep. boren<1:0> sboren device mode bor mode instruction execution upon: release of por or wake-up from sleep 11 x x active waits for bor ready (1) (borrdy = 1 ) 10 x awake active waits for bor ready (borrdy = 1 ) sleep disabled 01 1 x active waits for bor ready (1) (borrdy = 1 ) 0 xdisabled begins immediately (borrdy = x ) 00 x xdisabled note 1: in these specific cases, ?release of por? and ?wake-up from sleep?, there is no delay in start-up. the bor ready flag, (borrdy = 1 ), will be set before the cpu is ready to execute instructions because the bor circuit is forced on by the boren<1:0> bits.
? 2012 microchip technology inc. preliminary ds41624b-page 61 pic16(l)f1512/3 figure 6-2: brown -out situations register 6-1: borco n: brown-out reset control register r/w-1/u r/w-0/u u-0 u-0 u-0 u-0 u-0 r-q/u sboren borfs ? ? ? ? ? borrdy bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 sboren: software brown-out reset enable bit if boren <1:0> in configuration words ? 01 : sboren is read/write, but has no effect on the bor. if boren <1:0> in configuration words = 01 : 1 =bor enabled 0 =bor disabled bit 6 borfs: brown-out reset fast start bit (1) if boren<1:0> = 11 (always on) or boren<1:0> = 00 (always off) borfs is read/write, but has no effect. if boren <1:0> = 10 (disabled in sleep) or boren<1:0> = 01 (under software control): 1 = band gap is forced on always (covers sleep/wake-up/operating cases) 0 = band gap operates normally, and may turn off bit 5-1 unimplemented: read as ? 0 ? bit 0 borrdy: brown-out reset circuit ready status bit 1 = the brown-out reset circuit is active 0 = the brown-out reset circuit is inactive note 1: boren<1:0> bits are located in configuration words. t pwrt (1) v bor v dd internal reset v bor v dd internal reset t pwrt (1) < t pwrt t pwrt (1) v bor v dd internal reset note 1: t pwrt delay only if pwrte bit is programmed to ? 0 ?.
pic16(l)f1512/3 ds41624b-page 62 preliminary ? 2012 microchip technology inc. 6.3 low-power brown-out reset (lpbor) the low-power brown-out reset (lpbor) is an essential part of the reset subsystem. refer to figure 6-1 to see how the bor interacts with other modules. the lpbor is used to monitor the external v dd pin. when too low of a voltage is detected, the device is held in reset. when this occurs, a register bit (bor ) is changed to indicate that a bor reset has occurred. the same bit is set for both the bor and the lpbor. refer to register 6-2 . 6.3.1 enabling lpbor the lpbor is controlled by the lpboren bit of configuration words. when the device is erased, the lpbor module defaults to disabled. 6.3.1.1 lpbor module output the output of the lpbor module is a signal indicating whether or not a reset is to be asserted. this signal is to be or?d together with the reset signal of the bor module to provide the generic b or signal which goes to the pcon register and to the power control block. 6.4 mclr the mclr is an optional external input that can reset the device. the mclr function is controlled by the mclre bit of configuration words and the lvp bit of configuration words ( register 4-2 ). 6.4.1 mclr enabled when mclr is enabled and the pin is held low, the device is held in reset. the mclr pin is connected to v dd through an internal weak pull-up. the device has a noise filter in the mclr reset path. the filter will detect and ignore small pulses. 6.4.2 mclr disabled when mclr is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. see section 12.5 ?porte registers? for more information. 6.5 watchdog timer (wdt) reset the watchdog timer generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the to and pd bits in the status register are changed to indicate the wdt reset. see section 10.0 ?watchdog timer (wdt)? for more information. 6.6 reset instruction a reset instruction will cause a device reset. the ri bit in the pcon register will be set to ? 0 ?. see ta b l e 6 - 4 for default conditions after a reset instruction has occurred. 6.7 stack overflow/underflow reset the device can reset when the stack overflows or underflows. the stkovf or stkunf bits of the pcon register indicate the reset condition. these resets are enabled by setting the stvren bit in configuration words. see section 3.4.2 ?overflow/underflow reset? for more information. 6.8 programming mode exit upon exit of programming mode, the device will behave as if a por had just occurred. 6.9 power-up timer the power-up timer optionally delays device execution after a bor or por event. this timer is typically used to allow v dd to stabilize before allowing the device to start running. the power-up timer is controlled by the pwrte bit of configuration words. 6.10 start-up sequence upon the release of a por or bor, the following must occur before the device will begin executing: 1. power-up timer runs to completion (if enabled). 2. oscillator start-up timer runs to completion (if required for oscillator source). 3. mclr must be released (if enabled). the total time-out will vary based on oscillator configu- ration and power-up timer configuration. see section 5.0 ?oscillator module (with fail-safe clock monitor)? for more information. the power-up timer and oscillator start-up timer run independently of mclr reset. if mclr is kept low long enough, the power-up timer and oscillator start-up timer will expire. upon bringing mclr high, the device will begin execution immediately (see figure 6-3 ). this is useful for testing purposes or to synchronize more than one device operating in parallel. table 6-2: mclr configuration mclre lvp mclr 00 disabled 10 enabled x1 enabled note: a reset does not drive the mclr pin low.
? 2012 microchip technology inc. preliminary ds41624b-page 63 pic16(l)f1512/3 figure 6-3: reset start-up sequence t ost t mclr t pwrt v dd internal por power-up timer mclr internal reset oscillator modes oscillator start-up timer oscillator f osc internal oscillator oscillator f osc external clock (ec) clkin f osc external crystal
pic16(l)f1512/3 ds41624b-page 64 preliminary ? 2012 microchip technology inc. 6.11 determining the cause of a reset upon any reset, multiple bits in the status and pcon register are updated to indicate the cause of the reset. ta b l e 6 - 3 and tab l e 6 - 4 show the reset conditions of these registers. table 6-3: reset status bits and their significance table 6-4: reset condition for special registers (2) stkovf stkunf rwdt rmclr ri por bor to pd condition 0 0 1 1 10 x11 power-on reset 0 0 1 1 10 x0x illegal, to is set on por 0 0 1 1 10 xx0 illegal, pd is set on por 0 0 u 1 1u 011 brown-out reset u u 0 u uu u0u wdt reset u u u u uu u00 wdt wake-up from sleep u u u u uu u10 interrupt wake-up from sleep u u u 0 uu uuu mclr reset during normal operation u u u 0 uu u10 mclr reset during sleep u u u u 0 u u u u reset instruction executed 1 u u u uu uuu stack overflow reset (stvren = 1 ) u 1 u u uu uuu stack underflow reset (stvren = 1 ) condition program counter status register pcon register power-on reset 0000h ---1 1000 00-1 110x mclr reset during normal operation 0000h ---u uuuu uu-u 0uuu mclr reset during sleep 0000h ---1 0uuu uu-u 0uuu wdt reset 0000h ---0 uuuu uu-0 uuuu wdt wake-up from sleep pc + 1 ---0 0uuu uu-u uuuu brown-out reset 0000h ---1 1uuu 00-1 11u0 interrupt wake-up from sleep pc + 1 (1) ---1 0uuu uu-u uuuu reset instruction executed 0000h ---u uuuu uu-u u0uu stack overflow reset (stvren = 1 ) 0000h ---u uuuu 1u-u uuuu stack underflow reset (stvren = 1 ) 0000h ---u uuuu u1-u uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ? 0 ?. note 1: when the wake-up is due to an interrupt and global enable bit (gie) is set, the return address is pushed on the stack and pc is loaded with the interrupt vector (0004h) after execution of pc + 1. 2: if a status bit is not implemented, that bit will be read as ? 0 ?.
? 2012 microchip technology inc. preliminary ds41624b-page 65 pic16(l)f1512/3 6.12 power control (pcon) register the power control (pcon) register contains flag bits to differentiate between a: ? power-on reset (po r ) ? brown-out reset (bo r ) ? reset instruction reset (ri ) ?mclr reset (rmclr ) ? watchdog timer reset (rwdt ) ? stack underflow reset (stkunf) ? stack overflow reset (stkovf) the pcon register bits are shown in register 6-2 . register 6-2: pcon: power control register r/w/hs-0/q r/w/hs-0/q u-0 r/w/hc-1/q r/w/ hc-1/q r/w/hc-1/q r/w/hc-q/u r/w/hc-q/u stkovf stkunf ? r wdt rmclr ri por bor bit 7 bit 0 legend: hc = bit is cleared by hardware hs = bit is set by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -m/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 stkovf: stack overflow flag bit 1 = a stack overflow occurred 0 = a stack overflow has not occurred or cleared by firmware bit 6 stkunf: stack underflow flag bit 1 = a stack underflow occurred 0 = a stack underflow has not occurred or cleared by firmware bit 5 unimplemented: read as ? 0 ? bit 4 r wdt : watchdog timer reset flag bit 1 = a watchdog timer reset has not occurred or set to ? 1 ? by firmware 0 = a watchdog timer reset has occurred (cleared by hardware) bit 3 rmclr : mclr reset flag bit 1 = a mclr reset has not occurred or set to ? 1 ? by firmware 0 = a mclr reset has occurred (set to ? 0 ? in hardware when a mclr reset occurs) bit 2 ri : reset instruction flag bit 1 = a reset instruction has not been executed or set to ? 1 ? by firmware 0 = a reset instruction has been executed (cleared by hardware) bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a power-on reset or brown-out reset occurs)
pic16(l)f1512/3 ds41624b-page 66 preliminary ? 2012 microchip technology inc. table 6-5: summary of registers associated with resets name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page borcon sboren borfs ? ? ? ? ? borrdy 61 pcon stkovf stkunf ? r wdt rmclr ri por bor 65 status ? ? ?to pd z dc c 19 wdtcon ? ? wdtps<4:0> swdten 87 legend: ? = unimplemented, reads as ? 0 ?. shaded cells are not used by resets. note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation.
? 2012 microchip technology inc. preliminary ds41624b-page 67 pic16(l)f1512/3 7.0 interrupts the interrupt feature allows certain events to preempt normal program flow. firmware is used to determine the source of the interrupt and act accordingly. some interrupts can be configured to wake the mcu from sleep mode. this chapter contains the following information for interrupts: ? operation ? interrupt latency ? interrupts during sleep ?int pin ? automatic context saving many peripherals produce interrupts. refer to the corresponding chapters for details. a block diagram of the interrupt logic is shown in figure 7-1 . figure 7-1: interrupt logic tmr0if tmr0ie intf inte iocif iocie interrupt to cpu wake-up (if in sleep mode) gie (tmr1if) pir1<0> pirn<7> pien<7> peie peripheral interrupts (tmr1ie) pie1<0>
pic16(l)f1512/3 ds41624b-page 68 preliminary ? 2012 microchip technology inc. 7.1 operation interrupts are disabled upon any device reset. they are enabled by setting the following bits: ? gie bit of the intcon register ? interrupt enable bit(s) for the specific interrupt event(s) ? peie bit of the intcon register (if the interrupt enable bit of the interrupt event is contained in the piex register) the intcon, pir1 and pir2 registers record individual interrupts via interrupt flag bits. interrupt flag bits will be set, regardless of the status of the gie, peie and individual interrupt enable bits. the following events happen when an interrupt event occurs while the gie bit is set: ? current prefetched instruction is flushed ? gie bit is cleared ? current program counter (pc) is pushed onto the stack ? critical registers are automatically saved to the shadow registers (see section 7.5 ?automatic context saving? ) ? pc is loaded with the interrupt vector 0004h the firmware within the interrupt service routine (isr) should determine the source of the interrupt by polling the interrupt flag bits. the interrupt flag bits must be cleared before exiting the isr to avoid repeated interrupts. because the gie bit is cleared, any interrupt that occurs while executing the isr will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. the retfie instruction exits the isr by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the gie bit. for additional information on a specific interrupt?s operation, refer to its peripheral chapter. 7.2 interrupt latency interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. the latency for synchronous interrupts is three or four instruction cycles. for asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. see figure 7-2 and figure 7-3 for more details. note 1: individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: all interrupts will be ignored while the gie bit is cleared. any interrupt occurring while the gie bit is clear will be serviced when the gie bit is set again.
? 2012 microchip technology inc. preliminary ds41624b-page 69 pic16(l)f1512/3 figure 7-2: interrupt latency q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 clkout pc 0004h 0005h pc inst(0004h) nop gie q1 q2 q3 q4 q1 q2 q3 q4 1 cycle instruction at pc pc inst(0004h) nop 2 cycle instruction at pc fsr addr pc+1 pc+2 0004h 0005h pc inst(0004h) nop gie pc pc-1 3 cycle instruction at pc execute interrupt inst(pc) interrupt sampled during q1 inst(pc) pc-1 pc+1 nop pc new pc/ pc+1 0005h pc-1 pc+1/fsr addr 0004h nop interrupt gie interrupt inst(pc) nop nop fsr addr pc+1 pc+2 0004h 0005h pc inst(0004h) nop gie pc pc-1 3 cycle instruction at pc interrupt inst(pc) nop nop nop inst(0005h) execute execute execute
pic16(l)f1512/3 ds41624b-page 70 preliminary ? 2012 microchip technology inc. figure 7-3: int pin interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 osc1 clkout int pin intf gie instruction flow pc instruction fetched instruction executed interrupt latency pc pc + 1 pc + 1 0004h 0005h inst (0004h) inst (0005h) dummy cycle inst (pc) inst (pc + 1) inst (pc ? 1) inst (0004h) dummy cycle inst (pc) ? note 1: intf flag is sampled here (every q1). 2: asynchronous interrupt latency = 3-5 t cy . synchronous latency = 3-4 t cy , where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: clkout not available in all oscillator modes. 4: for minimum width of int pulse, refer to ac specifications in section 25.0 ?electrical specifications? . 5: intf is enabled to be set any time during the q4-q1 cycles. (1) (2) (3) (4) (5) (1)
? 2012 microchip technology inc. preliminary ds41624b-page 71 pic16(l)f1512/3 7.3 interrupts during sleep some interrupts can be used to wake from sleep. to wake from sleep, the peripheral must be able to operate without the system clock. the interrupt source must have the appropriate interrupt enable bit(s) set prior to entering sleep. on waking from sleep, if the gie bit is also set, the processor will branch to the interrupt vector. otherwise, the processor will continue executing instructions after the sleep instruction. the instruction directly after the sleep instruction will always be executed before branching to the isr. refer to the section 8.0 ?power- down mode (sleep)? for more details. 7.4 int pin the int pin can be used to generate an asynchronous edge-triggered interrupt. this interrupt is enabled by setting the inte bit of the intcon register. the intedg bit of the option_reg register determines on which edge the interrupt will occur. when the intedg bit is set, the rising edge will cause the interrupt. when the intedg bit is clear, the falling edge will cause the interrupt. the intf bit of the intcon register will be set when a valid edge appears on the int pin. if the gie and inte bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 automatic context saving upon entering an interrupt, the return pc address is saved on the stack. additionally, the following registers are automatically saved in the shadow registers: ? w register ? status register (except for to and pd ) ? bsr register ? fsr registers ? pclath register upon exiting the interrupt service routine, these registers are automatically restored. any modifications to these registers during the isr will be lost. if modifications to any of these registers are desired, the corresponding shadow register should be modified and the value will be restored when exiting the isr. the shadow registers are available in bank 31 and are readable and writable. depending on the user?s application, other registers may also need to be saved.
pic16(l)f1512/3 ds41624b-page 72 preliminary ? 2012 microchip technology inc. 7.6 interrupt control registers 7.6.1 intcon register the intcon register is a readable and writable register that contains the various enable and flag bits for tmr0 register overflow, interrupt-on-change and external int pin interrupts. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropri- ate interrupt flag bits are clear prior to enabling an interrupt. register 7-1: intcon: interrupt control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-0/0 gie peie tmr0ie inte iocie tmr0if intf iocif bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 gie: global interrupt enable bit 1 = enables all active interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all active peripheral interrupts 0 = disables all peripheral interrupts bit 5 tmr0ie: timer0 overflow interrupt enable bit 1 = enables the timer0 interrupt 0 = disables the timer0 interrupt bit 4 inte: int external interrupt enable bit 1 = enables the int external interrupt 0 = disables the int external interrupt bit 3 iocie: interrupt-on-change interrupt enable bit 1 = enables the interrupt-on-change 0 = disables the interrupt-on-change bit 2 tmr0if: timer0 overflow interrupt flag bit 1 = tmr0 register has overflowed 0 = tmr0 register did not overflow bit 1 intf: int external interrupt flag bit 1 = the int external interrupt occurred 0 = the int external interrupt did not occur bit 0 iocif: interrupt-on-change interrupt flag bit (1) 1 = when at least one of the interrupt-on-change pins changed state 0 = none of the interrupt-on-change pins have changed state note 1: the iocif flag bit is read-only and cleared when all the interrupt-on-change flags in the iocbf register have been cleared by software.
? 2012 microchip technology inc. preliminary ds41624b-page 73 pic16(l)f1512/3 7.6.2 pie1 register the pie1 register contains the interrupt enable bits, as shown in register 7-2 . note: bit peie of the intcon register must be set to enable any peripheral interrupt. register 7-2: pie1: peripheral interrupt enable register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 tmr1gie: timer1 gate interrupt enable bit 1 = enables the timer1 gate acquisition interrupt 0 = disables the timer1 gate acquisition interrupt bit 6 adie: a/d converter (adc) interrupt enable bit 1 = enables the adc interrupt 0 = disables the adc interrupt bit 5 rcie: usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie: usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3 sspie: synchronous serial port (mssp) interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2 ccp1ie: ccp1 interrupt enable bit 1 = enables the ccp1 interrupt 0 = disables the ccp1 interrupt bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the timer2 to pr2 match interrupt 0 = disables the timer2 to pr2 match interrupt bit 0 tmr1ie: timer1 overflow interrupt enable bit 1 = enables the timer1 overflow interrupt 0 = disables the timer1 overflow interrupt
pic16(l)f1512/3 ds41624b-page 74 preliminary ? 2012 microchip technology inc. 7.6.3 pie2 register the pie2 register contains the interrupt enable bits, as shown in register 7-3 . note: bit peie of the intcon register must be set to enable any peripheral interrupt. register 7-3: pie2: peripheral interrupt enable register 2 r/w-0/0 u-0 u-0 u-0 r/w-0/0 u-0 u-0 r/w-0/0 osfie ? ? ?bclie ? ? ccp2ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 osfie: oscillator fail interrupt enable bit 1 = enables the oscillator fail interrupt 0 = disables the oscillator fail interrupt bit 6-4 unimplemented: read as ? 0 ? bit 3 bclie: mssp bus collision interrupt enable bit 1 = enables the mssp bus collision interrupt 0 = disables the mssp bus collision interrupt bit 2-1 unimplemented: read as ? 0 ? bit 0 ccp2ie: ccp2 interrupt enable bit 1 = enables the ccp2 interrupt 0 = disables the ccp2 interrupt
? 2012 microchip technology inc. preliminary ds41624b-page 75 pic16(l)f1512/3 7.6.4 pir1 register the pir1 register contains the interrupt flag bits, as shown in register 7-4 . note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. register 7-4: pir1: peripheral interrupt request register 1 r/w-0/0 r/w-0/0 r-0/0 r-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 tmr1gif: timer1 gate interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 6 adif: a/d converter interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 5 rcif: usart receive interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 4 txif: usart transmit interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 3 sspif: synchronous serial port (mssp) interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 2 ccp1if: ccp1 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 1 tmr2if: timer2 to pr2 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 0 tmr1if: timer1 overflow interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending
pic16(l)f1512/3 ds41624b-page 76 preliminary ? 2012 microchip technology inc. 7.6.5 pir2 register the pir2 register contains the interrupt flag bits, as shown in register 7-5 . note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. register 7-5: pir2: peripheral interrupt request register 2 r/w-0/0 u-0 u-0 u-0 r/w-0/0 u-0 u-0 r/w-0/0 osfif ? ? ?bclif ? ? ccp2if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 osfif: oscillator fail interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 6-4 unimplemented: read as ? 0 ? bit 3 bclif: mssp bus collision interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 2-1 unimplemented: read as ? 0 ? bit 0 ccp2if: ccp2 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending
? 2012 microchip technology inc. preliminary ds41624b-page 77 pic16(l)f1512/3 table 7-1: summary of registers associated with interrupts name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 165 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pie2 osfie ? ? ?bclie ? ? ccp2ie 74 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 pir2 osfif ? ? ?bclif ? ? ccp2if 76 legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used by interrupts.
pic16(l)f1512/3 ds41624b-page 78 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds41624b-page 79 pic16(l)f1512/3 8.0 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. upon entering sleep mode, the following conditions exist: 1. wdt will be cleared but keeps running, if enabled for operation during sleep. 2. pd bit of the status register is cleared. 3. to bit of the status register is set. 4. cpu clock is disabled. 5. 31 khz lfintosc is unaffected and peripherals that operate from it may continue operation in sleep. 6. secondary oscillator is unaffected and peripherals that operate from it may continue operation in sleep. 7. adc is unaffected, if the dedicated frc clock is selected. 8. i/o ports maintain the status they had before sleep was executed (driving high, low or high- impedance). 9. resets other than wdt are not affected by sleep mode. refer to individual chapters for more details on peripheral operation during sleep. to minimize current consumption, the following conditions should be considered: ? i/o pins should not be floating ? external circuitry sinking current from i/o pins ? internal circuitry sourcing current from i/o pins ? current draw from pins with internal weak pull-ups ? modules using 31 khz lfintosc ? modules using secondary oscillator i/o pins that are high-impedance inputs should be pulled to v dd or v ss externally to avoid switching currents caused by floating inputs. examples of internal circuitry that might be sourcing current include the fvr module. see section 14.0 ?fixed voltage reference (fvr)? for more information on this module. 8.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin, if enabled 2. bor reset, if enabled 3. por reset 4. watchdog timer, if enabled 5. any external interrupt 6. interrupts by peripherals capable of running during sleep (see individual peripheral for more information) the first three events will cause a device reset. the last three events are considered a continuation of program execution. to determine whether a device reset or wake-up event occurred, refer to section 6.11 ?determining the cause of a reset? . when the sleep instruction is being executed, the next instruction (pc + 1) is prefetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. wake-up will occur regardless of the state of the gie bit. if the gie bit is disabled, the device continues execution at the instruction after the sleep instruction. if the gie bit is enabled, the device executes the instruction after the sleep instruction, the device will then call the interrupt service routine. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. the wdt is cleared when the device wakes up from sleep, regardless of the source of wake-up.
pic16(l)f1512/3 ds41624b-page 80 preliminary ? 2012 microchip technology inc. 8.1.1 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction - sleep instruction will execute as a nop - wdt and wdt prescaler will not be cleared -to bit of the status register will not be set -pd bit of the status register will not be cleared ? if the interrupt occurs during or after the execution of a sleep instruction - sleep instruction will be completely executed - device will immediately wake-up from sleep - wdt and wdt prescaler will be cleared -to bit of the status register will be set -pd bit of the status register will be cleared even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop . figure 8-1: wake-up from sleep through interrupt q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 clkin (1) clkout (2) interrupt flag gie bit (intcon reg.) instruction flow pc instruction fetched instruction executed pc pc + 1 pc + 2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (4) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) forced nop pc + 2 0004h 0005h forced nop t1 osc (3) pc + 2 note 1: external clock. high, medium, low mode assumed. 2: clkout is shown here for timing reference. 3: t1 osc ; see section 25.0 ?electrical specifications? . 4: gie = 1 assumed. in this case after wake-up, the processor calls the isr at 0004h. if gie = 0 , execution will continue in-line.
? 2012 microchip technology inc. preliminary ds41624b-page 81 pic16(l)f1512/3 8.2 low-power sleep mode the pic16f1512/3 device contains an internal low dropout (ldo) voltage regulator, which allows the device i/o pins to operate at voltages up to 5.5v while the internal device logic operates at a lower voltage. the ldo and its associated reference circuitry must remain active when the device is in sleep mode. the pic16f1512/3 allows the user to optimize the operating current in sleep, depending on the application requirements. a low-power sleep mode can be selected by setting the vregpm bit of the vregcon register. with this bit set, the ldo and reference circuitry are placed in a low-power state when the device is in sleep. 8.2.1 sleep current vs. wake-up time in the default operating mode, the ldo and reference circuitry remain in the normal configuration while in sleep. the device is able to exit sleep mode quickly since all circuits remain active. in low-power sleep mode, when waking up from sleep, an extra delay time is required for these circuits to return to the normal configuration and stabilize. the low-power sleep mode is beneficial for applications that stay in sleep mode for long periods of time. the normal mode is beneficial for applications that need to wake from sleep quickly and frequently. 8.2.2 peripheral usage in sleep some peripherals that can operate in sleep mode will not operate properly with the low-power sleep mode selected. the ldo will remain in the normal power mode when those peripherals are enabled. the low- power sleep mode is intended for use with these peripherals: ? brown-out reset (bor) ? watchdog timer (wdt) ? external interrupt pin/interrupt-on-change pins ? timer1 (with external clock source) ? ccp (capture mode) 8.3 power control registers note: the pic16lf1512/3 does not have a configurable low-power sleep mode. pic16lf1512/3 is an unregulated device and is always in the lowest power state when in sleep, with no wake-up time penalty. this device has a lower maximum v dd and i/o voltage than the pic16f1512/3. see section 25.0 ?electrical specifications? for more information. register 8-1: vregcon: voltag e regulator control register (1) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0/0 r/w-1/1 ? ? ? ? ? ?vregpm reserved bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-2 unimplemented: read as ? 0 ? bit 1 vregpm: voltage regulator power mode selection bit 1 = low-power sleep mode enabled in sleep (2) draws lowest current in sleep, slower wake-up 0 = normal-power mode enabled in sleep (2) draws higher current in sleep, faster wake-up bit 0 reserved: read as ? 1 ?. maintain this bit set. note 1: pic16f1512/3 only. 2: see section 25.0 ?electrical specifications? .
pic16(l)f1512/3 ds41624b-page 82 preliminary ? 2012 microchip technology inc. table 8-1: summary of registers as sociated with power-down mode name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 iocbf iocbf7 iocbf6 iocbf5 iocbf4 iocbf3 iocbf2 iocbf1 iocbf0 123 iocbn iocbn7 iocbn6 iocbn5 iocbn 4 iocbn3 iocbn2 iocbn1 iocbn0 123 iocbp iocbp7 iocbp6 iocbp5 iocbp 4 iocbp3 iocbp2 iocbp1 iocbp0 123 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pie2 osfie ? ? ? bclie ? ? ccp2ie 74 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 pir2 osfif ? ? ? bclif ? ? ccp2if 76 status ? ? ?to pd z dc c 19 vregcon (1) ? ? ? ? ? ?vregpm reserved 81 wdtcon ? ? wdtps<4:0> swdten 87 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used in power-down mode. note 1: pic16f1512/3 only.
? 2012 microchip technology inc. preliminary ds41624b-page 83 pic16(l)f1512/3 9.0 low dropout (ldo) voltage regulator the pic16f1512/3 has an internal low dropout regulator (ldo) which provides operation above 3.6v. the ldo regulates a voltage for the internal device logic while permitting the v dd and i/o pins to operate at a higher voltage. there is no user enable/disable control available for the ldo, it is always active. the pic16lf1512/3 operates at a maximum v dd of 3.6v and does not incorporate an ldo. a device i/o pin may be configured as the ldo voltage output, identified as the v cap pin. although not required, an external low-esr capacitor may be connected to the v cap pin for additional regulator stability. the vcapen bit of configuration words determines which pin is assigned as the v cap pin. refer to tab le 9 - 1 . on power-up, the external capacitor will load the ldo voltage regulator. to prevent erroneous operation, the device is held in reset while a constant current source charges the external capacitor. after the cap is fully charged, the device is released from reset. for more information on the constant current rate, refer to the ldo regulator characteristics table in section 25.0 ?electrical specifications? . table 9-2: summary of conf iguration word with ldo table 9-1: vcapen select bit vcape n pin 0 ra5 name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config2 13:8 lvp debug lpbor borv stvren ? 40 7:0 ? ? ? vcapen ? ? wrt<1:0> legend: ? = unimplemented locations read as ? 0 ?. shaded cells are not used by ldo. note 1: pic16f1512/3 only.
pic16(l)f1512/3 ds41624b-page 84 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds41624b-page 85 pic16(l)f1512/3 10.0 watchdog timer (wdt) the watchdog timer is a system timer that generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the watchdog timer is typically used to recover the system from unexpected events. the wdt has the following features: ? independent clock source ? multiple operating modes - wdt is always on - wdt is off when in sleep - wdt is controlled by software - wdt is always off ? configurable time-out period is from 1 ms to 256 seconds (nominal) ? multiple reset conditions ? operation during sleep figure 10-1: watchdog ti mer block diagram lfintosc 23-bit programmable prescaler wdt wdt time-out wdtps<4:0> swdten sleep wdte<1:0> = 11 wdte<1:0> = 01 wdte<1:0> = 10
pic16(l)f1512/3 ds41624b-page 86 preliminary ? 2012 microchip technology inc. 10.1 independent clock source the wdt derives its time base from the 31 khz lfintosc internal oscillator. time intervals in this chapter are based on a nominal interval of 1 ms. see section 25.0 ?electrical specifications? for the lfintosc tolerances. 10.2 wdt operating modes the watchdog timer module has four operating modes controlled by the wdte<1:0> bits in configuration words. see table 10-1 . 10.2.1 wdt is always on when the wdte bits of configuration words are set to ? 11 ?, the wdt is always on. wdt protection is active during sleep. 10.2.2 wdt is off in sleep when the wdte bits of configuration words are set to ? 10 ?, the wdt is on, except in sleep. wdt protection is not active during sleep. 10.2.3 wdt controlled by software when the wdte bits of configuration words are set to ? 01 ?, the wdt is controlled by the swdten bit of the wdtcon register. wdt protection is unchanged by sleep. see table 10-1 for more details. table 10-1: wdt operating modes 10.3 time-out period the wdtps bits of the wdtcon register set the time-out period from 1 ms to 256 seconds (nominal). after a reset, the default time-out period is two seconds. 10.4 clearing the wdt the wdt is cleared when any of the following conditions occur: ?any reset ? clrwdt instruction is executed ? device enters sleep ? device wakes up from sleep ? oscillator fail ? wdt is disabled ? oscillator start-up timer (ost) is running see table 10-2 for more information. 10.5 operation during sleep when the device enters sleep, the wdt is cleared. if the wdt is enabled during sleep, the wdt resumes counting. when the device exits sleep, the wdt is cleared again. the wdt remains clear until the ost, if enabled, completes. see section 5.0 ?oscillator module (with fail-safe clock monitor)? for more information on the ost. when a wdt time-out occurs while the device is in sleep, no reset is generated. instead, the device wakes up and resumes operation. the to and pd bits in the status register are changed to indicate the event. see section 3.0 ?memory organization? and the status register ( register 3-1 ) for more information. wdte<1:0> swdten device mode wdt mode 11 x xactive 10 x awake active sleep disabled 01 1 x active 0 disabled 00 x x disabled table 10-2: wdt clearing conditions conditions wdt wdte<1:0> = 00 cleared wdte<1:0> = 01 and swdten = 0 wdte<1:0> = 10 and enter sleep clrwdt command oscillator fail detected exit sleep + system clock = sosc, extrc, intosc, extclk exit sleep + system clock = xt, hs, lp cleared until the end of ost change intosc divider (ircf bits) unaffected
? 2012 microchip technology inc. preliminary ds41624b-page 87 pic16(l)f1512/3 10.6 watchdog control register register 10-1: wdtcon: wat chdog timer control register u-0 u-0 r/w-0/0 r/w-1/1 r/w-0/0 r/w-1/1 r/w-1/1 r/w-0/0 ? ? wdtps<4:0> swdten bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -m/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-1 wdtps<4:0>: watchdog timer period select bits (1) bit value = prescale rate 11111 = reserved. results in minimum interval (1:32) ? ? ? 10011 = reserved. results in minimum interval (1:32) 10010 = 1:8388608 (2 23 ) (interval 256s nominal) 10001 = 1:4194304 (2 22 ) (interval 128s nominal) 10000 = 1:2097152 (2 21 ) (interval 64s nominal) 01111 = 1:1048576 (2 20 ) (interval 32s nominal) 01110 = 1:524288 (2 19 ) (interval 16s nominal) 01101 = 1:262144 (2 18 ) (interval 8s nominal) 01100 = 1:131072 (2 17 ) (interval 4s nominal) 01011 = 1:65536 (interval 2s nominal) (reset value) 01010 = 1:32768 (interval 1s nominal) 01001 = 1:16384 (interval 512 ms nominal) 01000 = 1:8192 (interval 256 ms nominal) 00111 = 1:4096 (interval 128 ms nominal) 00110 = 1:2048 (interval 64 ms nominal) 00101 = 1:1024 (interval 32 ms nominal) 00100 = 1:512 (interval 16 ms nominal) 00011 = 1:256 (interval 8 ms nominal) 00010 = 1:128 (interval 4 ms nominal) 00001 = 1:64 (interval 2 ms nominal) 00000 = 1:32 (interval 1 ms nominal) bit 0 swdten: software enable/disable for watchdog timer bit if wdte<1:0> = 00 : this bit is ignored. if wdte<1:0> = 01 : 1 = wdt is turned on 0 = wdt is turned off if wdte<1:0> = 1x : this bit is ignored. note 1: times are approximate. wdt time is based on 31 khz lfintosc.
pic16(l)f1512/3 ds41624b-page 88 preliminary ? 2012 microchip technology inc. table 10-3: summary of registers associated with watchdog timer table 10-4: summary of configurat ion word with watchdog timer name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page osccon ? ircf<3:0> ?scs<1:0> 56 status ? ? ?to pd z dc c 19 wdtcon ? ? wdtps<4:0> swdten 87 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by watchdog timer . name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? fcmen ieso clkouten boren<1:0> ? 38 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by watchdog timer.
? 2012 microchip technology inc. preliminary ds41624b-page 89 pic16(l)f1512/3 11.0 flash program memory control the flash program memory is readable and writable during normal operation over the full v dd range. program memory is indirectly addressed using special function registers (sfrs). the sfrs used to access program memory are: ?pmcon1 ?pmcon2 ?pmdatl ?pmdath ? pmadrl ?pmadrh when accessing the program memory, the pmdath:pmdatl register pair forms a 2-byte word that holds the 14-bit data for read/write, and the pmadrh:pmadrl register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read. the write time is controlled by an on-chip timer. the write/ erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device. the flash program memory can be protected in two ways; by code protection (cp bit in configuration words) and write protection (wrt<1:0> bits in configuration words). code protection (cp = 0 ) (1) , disables access, reading and writing, to the flash program memory via external device programmers. code protection does not affect the self-write and erase functionality. code protection can only be reset by a device programmer performing a bulk erase to the device, clearing all flash program memory, configuration bits and user ids. write protection prohibits self-write and erase to a portion or all of the flash program memory as defined by the bits wrt<1:0>. write protection does not affect a device programmers ability to read, write or erase the device. 11.1 pmadrl and pmadrh registers the pmadrh:pmadrl register pair can address up to a maximum of 32k words of program memory. when selecting a program address value, the msb of the address is written to the pmadrh register and the lsb is written to the pmadrl register. 11.1.1 pmcon1 and pmcon2 registers pmcon1 is the control register for flash program memory accesses. control bits rd and wr initiate read and write, respectively. these bits cannot be cleared, only set, in software. they are cleared by hardware at completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental, premature termination of a write operation. the wren bit, when set, will allow a write operation to occur. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a reset during normal operation. in these situations, following reset, the user can check the wrerr bit and execute the appropriate error handling routine. the pmcon2 register is a write-only register. attempting to read the pmcon2 register will return all ? 0 ?s. to enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the pmcon2 register. the required unlock sequence prevents inadvertent writes to the program memory write latches and flash program memory. 11.2 flash program memory overview it is important to understand the flash program memory structure for erase and programming operations. flash program memory is arranged in rows. a row consists of a fixed number of 14-bit program memory words. a row is the minimum size that can be erased by user software. after a row has been erased, the user can reprogram all or a portion of this row. data to be written into the program memory row is written to 14-bit wide data write latches. these write latches are not directly accessible to the user, but may be loaded via sequential writes to the pmdath:pmdatl register pair. see table 11-1 for erase row size and the number of write latches for flash program memory. note 1: code protection of the entire flash program memory array is enabled by clearing the cp bit of configuration words. note: if the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in ram prior to the erase. then, new data and retained data can be written into the write latches to reprogram the row of flash program memory. however, any unprogrammed locations can be written without first erasing the row. in this case, it is not necessary to save and rewrite the other previously programmed locations.
pic16(l)f1512/3 ds41624b-page 90 preliminary ? 2012 microchip technology inc. 11.2.1 reading the flash program memory to read a program memory location, the user must: 1. write the desired address to the pmadrh:pmadrl register pair. 2. clear the cfgs bit of the pmcon1 register. 3. then, set control bit rd of the pmcon1 register. once the read control bit is set, the program memory flash controller will use the second instruction cycle to read the data. this causes the second instruction immediately following the ? bsf pmcon1,rd ? instruction to be ignored. the data is available in the very next cycle, in the pmdath:pmdatl register pair; therefore, it can be read as two bytes in the following instructions. pmdath:pmdatl register pair will hold this value until another read or until it is written to by the user. figure 11-1: flash program memory read flowchart table 11-1: flash memory organization by device device row erase (words) write latches (words) pic16(l)f1516 32 32 pic16(l)f1517 pic16(l)f1518 pic16(l)f1519 note: the two instructions following a program memory read are required to be nop s. this prevents the user from executing a two-cycle instruction on the next instruction after the rd bit is set. start read operation select program or configuration memory (cfgs) select word address (pmadrh:pmadrl) end read operation instruction fetched ignored nop execution forced instruction fetched ignored nop execution forced initiate read operation (rd = 1 ) data read now in pmdath:pmdatl
? 2012 microchip technology inc. preliminary ds41624b-page 91 pic16(l)f1512/3 figure 11-2: flash program me mory read cycle execution example 11-1: flash program memory read q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bsf pmcon1,rd executed here instr(pc + 1) executed here pc pc + 1 pmadrh,pmadrl pc+3 pc + 5 flash addr rd bit pmdath,pmdatl pc + 3 pc + 4 instr (pc + 1) instr(pc - 1) executed here instr(pc + 3) executed here instr(pc + 4) executed here flash data pmdath pmdatl register instr (pc) instr (pc + 3) instr (pc + 4) instruction ignored forced nop instr(pc + 2) executed here instruction ignored forced nop * this code block will read 1 word of program * memory at the memory address: prog_addr_hi : prog_addr_lo * data will be returned in the variables; * prog_data_hi, prog_data_lo banksel pmadrl ; select bank for pmcon registers movlw prog_addr_lo ; movwf pmadrl ; store lsb of address movlw prog_addr_hi ; movwl pmadrh ; store msb of address bcf pmcon1,cfgs ; do not select configuration space bsf pmcon1,rd ; initiate read nop ; ignored ( figure 11-2 ) nop ; ignored ( figure 11-2 ) movf pmdatl,w ; get lsb of word movwf prog_data_lo ; store in user location movf pmdath,w ; get msb of word movwf prog_data_hi ; store in user location
pic16(l)f1512/3 ds41624b-page 92 preliminary ? 2012 microchip technology inc. 11.2.2 flash memory unlock sequence the unlock sequence is a mechanism that protects the flash program memory from unintended self-write programming or erasing. the sequence must be executed and completed without interruption to successfully complete any of the following operations: ?row erase ? load program memory write latches ? write of program memory write latches to program memory ? write of program memory write latches to user ids the unlock sequence consists of the following steps: 1. write 55h to pmcon2 2. write aah to pmcon2 3. set the wr bit in pmcon1 4. nop instruction 5. nop instruction once the wr bit is set, the processor will always force two nop instructions. when an erase row or program row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction. when the operation is loading the program memory write latches, the processor will always force the two nop instructions and continue uninterrupted with the next instruction. since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. figure 11-3: flash program memory unlock sequence flowchart write 055h to pmcon2 start unlock sequence write 0aah to pmcon2 initiate write or erase operation (wr = 1 ) instruction fetched ignored nop execution forced end unlock sequence instruction fetched ignored nop execution forced
? 2012 microchip technology inc. preliminary ds41624b-page 93 pic16(l)f1512/3 11.2.3 erasing flash program memory while executing code, program memory can only be erased by rows. to erase a row: 1. load the pmadrh:pmadrl register pair with any address within the row to be erased. 2. clear the cfgs bit of the pmcon1 register. 3. set the free and wren bits of the pmcon1 register. 4. write 55h, then aah, to pmcon2 (flash programming unlock sequence). 5. set control bit wr of the pmcon1 register to begin the erase operation. see example 11-2 . after the ? bsf pmcon1,wr ? instruction, the processor requires two cycles to set up the erase operation. the user must place two nop instructions immediately following the wr bit set instruction. the processor will halt internal operations for the typical 2 ms erase time. this is not sleep mode as the clocks and peripherals will continue to run. after the erase cycle, the processor will resume operation with the third instruction after the pmcon1 write instruction. figure 11-4: flash program memory erase flowchart disable interrupts (gie = 0 ) start erase operation select program or configuration memory (cfgs) select row address (pmadrh:pmadrl) select erase operation (free = 1 ) enable write/erase operation (wren = 1 ) unlock sequence (figure x-x) disable write/erase operation (wren = 0 ) re-enable interrupts (gie = 1 ) end erase operation cpu stalls while erase operation completes (2ms typical) figure 11-3
pic16(l)f1512/3 ds41624b-page 94 preliminary ? 2012 microchip technology inc. example 11-2: erasing one row of program memory ; this row erase routine assumes the following: ; 1. a valid address within the erase row is loaded in addrh:addrl ; 2. addrh and addrl are located in shared data memory 0x70 - 0x7f (common ram) bcf intcon,gie ; disable ints so required sequences will execute properly banksel pmadrl movf addrl,w ; load lower 8 bits of erase address boundary movwf pmadrl movf addrh,w ; load upper 6 bits of erase address boundary movwf pmadrh bcf pmcon1,cfgs ; not configuration space bsf pmcon1,free ; specify an erase operation bsf pmcon1,wren ; enable writes movlw 55h ; start of required sequence to initiate erase movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin erase nop ; nop instructions are forced as processor starts nop ; row erase of program memory. ; ; the processor stalls until the erase process is complete ; after erase processor continues with 3rd instruction bcf pmcon1,wren ; disable writes bsf intcon,gie ; enable interrupts required sequence
? 2012 microchip technology inc. preliminary ds41624b-page 95 pic16(l)f1512/3 11.2.4 writing to flash program memory program memory is programmed using the following steps: 1. load the address in pmadrh:pmadrl of the row to be programmed. 2. load each write latch with data. 3. initiate a programming operation. 4. repeat steps 1 through 3 until all data is written. before writing to program memory, the word(s) to be written must be erased or previously unwritten. program memory can only be erased one row at a time. no automatic erase occurs upon the initiation of the write. program memory can be written one or more words at a time. the maximum number of words written at one time is equal to the number of write latches. see figure 11-5 (row writes to program memory with 32 write latches) for more details. the write latches are aligned to the flash row address boundary defined by the upper 10-bits of pmadrh:pmadrl, (pmadrh<6:0>:pmadrl<7:5>) with the lower 5-bits of pmadrl, (pmadrl<4:0>) determining the write latch being loaded. write opera- tions do not cross these boundaries. at the completion of a program memory write operation, the data in the write latches is reset to contain 0x3fff. the following steps should be completed to load the write latches and program a row of program memory. these steps are divided into two parts. first, each write latch is loaded with data from the pmdath:pmdatl using the unlock sequence with lwlo = 1 . when the last word to be loaded into the write latch is ready, the lwlo bit is cleared and the unlock sequence executed. this initiates the programming operation, writing all the latches into flash program memory. 1. set the wren bit of the pmcon1 register. 2. clear the cfgs bit of the pmcon1 register. 3. set the lwlo bit of the pmcon1 register. when the lwlo bit of the pmcon1 register is ? 1 ?, the write sequence will only load the write latches and will not initiate the write to flash program memory. 4. load the pmadrh:pmadrl register pair with the address of the location to be written. 5. load the pmdath:pmdatl register pair with the program memory data to be written. 6. execute the unlock sequence ( section 11.2.2 ?flash memory unlock sequence? ). the write latch is now loaded. 7. increment the pmadrh:pmadrl register pair to point to the next location. 8. repeat steps 5 through 7 until all but the last write latch has been loaded. 9. clear the lwlo bit of the pmcon1 register. when the lwlo bit of the pmcon1 register is ? 0 ?, the write sequence will initiate the write to flash program memory. 10. load the pmdath:pmdatl register pair with the program memory data to be written. 11. execute the unlock sequence ( section 11.2.2 ?flash memory unlock sequence? ). the entire program memory latch content is now written to flash program memory. an example of the complete write sequence is shown in example 11-3 . the initial address is loaded into the pmadrh:pmadrl register pair; the data is loaded using indirect addressing. note: the special unlock sequence is required to load a write latch with data or initiate a flash programming operation. if the unlock sequence is interrupted, writing to the latches or program memory will not be initiated. note: the program memory write latches are reset to the blank state (0x3fff) at the completion of every write or erase operation. as a result, it is not necessary to load all the program memory write latches. unloaded latches will remain in the blank state.
pic16(l)f1512/3 ds41624b-page 96 preliminary ? 2012 microchip technology inc. figure 11-5: block writes to flash program memory with 32 write latches pmdath pmdatl 7 5 0 7 0 6 8 14 14 14 write latch #31 1fh 14 14 pmadrh pmadrl 7 6 0 7 5 4 0 program memory write latches 14 14 14 5 10 pmadrh<6:0> :pmadrl<7:5> flash program memory row row address decode addr write latch #30 1eh write latch #1 01h write latch #0 00h addr addr addr 000h 001fh 001eh 0000h 0001h 001h 003fh 003eh 0020h 0021h 002h 005fh 005eh 0040h 0041h 3feh 7fdfh 7fdeh 7fc0h 7fc1h 3ffh 7fffh 7ffeh 7fe0h 7fe1h 14 r9 r8 r7 r6 r5 r4 r3 - r1 r0 c4 c3 c2 c1 c0 r2 pmadrl<4:0> 400h 8009h-801fh 8000h-8003h configuration words user id 0-3 8007h-8008h 8006h deviceid revid reserved 8004h-8005h reserved configuration memory cfgs = 0 cfgs = 1 - -
? 2012 microchip technology inc. preliminary ds41624b-page 97 pic16(l)f1512/3 figure 11-6: flash program memory write flowchart disable interrupts (gie = 0 ) start write operation select program or config. memory (cfgs) select row address (pmadrh:pmadrl) select write operation (free = 0 ) enable write/erase operation (wren = 1 ) unlock sequence (figure x-x) disable write/erase operation (wren = 0 ) re-enable interrupts (gie = 1 ) end write operation no delay when writing to program memory latches determine the number of words to be written into the program or configuration memory. the number of words cannot exceed the number of words per row. (word_cnt) load the value to write (pmdath:pmdatl) update the word counter (word_cnt--) last word to write ? increment address (pmadrh:pmadrl++) unlock sequence (figure x-x) cpu stalls while write operation completes (2ms typical) load write latches only (lwlo = 1 ) write latches to flash (lwlo = 0 ) no yes figure 11-3 figure 11-3
pic16(l)f1512/3 ds41624b-page 98 preliminary ? 2012 microchip technology inc. example 11-3: writing to flash program memory ; this write routine assumes the following: ; 1. 64 bytes of data are loaded, starting at the address in data_addr ; 2. each word of data to be written is made up of two adjacent bytes in data_addr, ; stored in little endian format ; 3. a valid starting address (the least significant bits = 00000) is loaded in addrh:addrl ; 4. addrh and addrl are located in shared data memory 0x70 - 0x7f (common ram) ; bcf intcon,gie ; disable ints so required sequences will execute properly banksel pmadrh ; bank 3 movf addrh,w ; load initial address movwf pmadrh ; movf addrl,w ; movwf pmadrl ; movlw low data_addr ; load initial data address movwf fsr0l ; movlw high data_addr ; load initial data address movwf fsr0h ; bcf pmcon1,cfgs ; not configuration space bsf pmcon1,wren ; enable writes bsf pmcon1,lwlo ; only load write latches loop moviw fsr0++ ; load first data byte into lower movwf pmdatl ; moviw fsr0++ ; load second data byte into upper movwf pmdath ; movf pmadrl,w ; check if lower bits of address are '00000' xorlw 0x1f ; check if we're on the last of 32 addresses andlw 0x1f ; btfsc status,z ; exit if last of 32 words, goto start_write ; movlw 55h ; start of required write sequence: movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin write nop ; nop instructions are forced as processor ; loads program memory write latches nop ; incf pmadrl,f ; still loading latches increment address goto loop ; write next latches start_write bcf pmcon1,lwlo ; no more loading latches - actually start flash program ; memory write movlw 55h ; start of required write sequence: movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin write nop ; nop instructions are forced as processor writes ; all the program memory write latches simultaneously nop ; to program memory. ; after nops, the processor ; stalls until the self-write process in complete ; after write processor continues with 3rd instruction bcf pmcon1,wren ; disable writes bsf intcon,gie ; enable interrupts required sequence required sequence
? 2012 microchip technology inc. preliminary ds41624b-page 99 pic16(l)f1512/3 11.3 modifying flash program memory when modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a ram image. program memory is modified using the following steps: 1. load the starting address of the row to be modified. 2. read the existing data from the row into a ram image. 3. modify the ram image to contain the new data to be written into program memory. 4. load the starting address of the row to be rewritten. 5. erase the program memory row. 6. load the write latches with data from the ram image. 7. initiate a programming operation. figure 11-7: flash program memory modify flowchart start modify operation read operation (figure x.x) erase operation (figure x.x) modify image the words to be modified are changed in the ram image end modify operation write operation use ram image (figure x.x) an image of the entire row read must be stored in ram figure 11-2 figure 11-4 figure 11-5
pic16(l)f1512/3 ds41624b-page 100 preliminary ? 2012 microchip technology inc. 11.4 user id, device id and configuration word access instead of accessing program memory, the user id?s, device id/revision id and configuration words can be accessed when cfgs = 1 in the pmcon1 register. this is the region that would be pointed to by pc<15> = 1 , but not all addresses are accessible. different access may exist for reads and writes. refer to table 11-2 . when read access is initiated on an address outside the parameters listed in ta b l e 11 - 2 , the pmdath:pmdatl register pair is cleared, reading back ? 0 ?s. table 11-2: user id, device id and configuration word access (cfgs = 1 ) example 11-4: configuration word and device id access address function read access write access 8000h-8003h user ids yes yes 8006h device id/revision id yes no 8007h-8008h configuration words 1 and 2 yes no * this code block will read 1 word of program memory at the memory address: * prog_addr_lo (must be 00h-08h) data will be returned in the variables; * prog_data_hi, prog_data_lo banksel pmadrl ; select correct bank movlw prog_addr_lo ; movwf pmadrl ; store lsb of address clrf pmadrh ; clear msb of address bsf pmcon1,cfgs ; select configuration space bcf intcon,gie ; disable interrupts bsf pmcon1,rd ; initiate read nop ; executed (see figure 11-2 ) nop ; ignored (see figure 11-2 ) bsf intcon,gie ; restore interrupts movf pmdatl,w ; get lsb of word movwf prog_data_lo ; store in user location movf pmdath,w ; get msb of word movwf prog_data_hi ; store in user location
? 2012 microchip technology inc. preliminary ds41624b-page 101 pic16(l)f1512/3 11.5 write verify it is considered good programming practice to verify that program memory writes agree with the intended value. since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in ram after the last write is complete. figure 11-8: flash program memory verify flowchart start verify operation read operation (figure x.x) end verify operation this routine assumes that the last row of data written was from an image saved in ram. this image will be used to verify the data currently stored in flash program memory. pmdat = ram image ? last word ? fail verify operation no yes yes no figure 11-2
pic16(l)f1512/3 ds41624b-page 102 preliminary ? 2012 microchip technology inc. 11.6 flash program memory control registers register 11-1: pmdatl: program memory data low byte register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u pmdat<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 pmdat<7:0> : read/write value for least significant bits of program memory register 11-2: pmdath: program memory data high byte register u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u ? ? pmdat<13:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 pmdat<13:8> : read/write value for most significant bits of program memory register 11-3: pmadrl: program memory address low byte register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 pmadr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 pmadr<7:0> : specifies the least significant bits for program memory address register 11-4: pmadrh: program memory address high byte register u-1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? pmadr<14:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 1 ? bit 6-0 pmadr<14:8> : specifies the most significant bits for program memory address
? 2012 microchip technology inc. preliminary ds41624b-page 103 pic16(l)f1512/3 register 11-5: pmcon1: progra m memory control 1 register u-1 (1) r/w-0/0 r/w-0/0 r/w/hc-0/0 r/w/hc-x/q (2) r/w-0/0 r/s/hc-0/0 r/s/hc-0/0 ? cfgs lwlo free wrerr wren wr rd bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cl eared hc = bit is cleared by hardware bit 7 unimplemented: read as ? 1 ? bit 6 cfgs: configuration select bit 1 = access configuration, user id and device id registers 0 = access flash program memory bit 5 lwlo: load write latches only bit (3) 1 = only the addressed program memory write latch is loaded/updated on the next wr command 0 = the addressed program memory write latch is loaded/ updated and a write of all program memory write latches will be initiated on the next wr command bit 4 free: program flash erase enable bit 1 = performs an erase operation on the next wr command (hardware cleared upon completion) 0 = performs a write operation on the next wr command bit 3 wrerr: program/erase error flag bit 1 = condition indicates an improper program or erase sequenc e attempt or termination (bit is set automatically on any set attempt (write ? 1 ?) of the wr bit). 0 = the program or erase operation completed normally. bit 2 wren: program/erase enable bit 1 = allows program/erase cycles 0 = inhibits programming/erasing of program flash bit 1 wr: write control bit 1 = initiates a program flash program/erase operation. the operation is self-timed and the bit is cl eared by hardware once operation is complete. the wr bit can only be set (not cleared) in software. 0 = program/erase operation to the flash is complete and inactive. bit 0 rd: read control bit 1 = initiates a program flash read. read takes one cycle. rd is cleared in hardware. the rd bit can only be set (not cleared) in software. 0 = does not initiate a program flash read. note 1: unimplemented bit, read as ? 1 ?. 2: the wrerr bit is automatically set by hardware when a pr ogram memory write or erase operation is started (wr = 1 ) . 3: the lwlo bit is ignored during a progr am memory erase operation (free = 1 ).
pic16(l)f1512/3 ds41624b-page 104 preliminary ? 2012 microchip technology inc. table 11-3: summary of registers as sociated with flash program memory table 11-4: summary of configuration word with flash program memory register 11-6: pmcon2: progra m memory control 2 register w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 program memory control register 2 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 flash memory unlock pattern bits to unlock writes, a 55h must be written first, followed by an aah, before setting the wr bit of the pmcon1 register. the value written to this register is used to unlock the writes. there are specific timing requirements on these writes. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pmcon1 ? cfgs lwlo free wrerr wren wr rd 103 pmcon2 program memory control register 2 104 pmadrl pmadrl<7:0> 102 pmadrh ? pmadrh<6:0> 102 pmdatl pmdatl<7:0> 102 pmdath ? ? pmdath<5:0> 102 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by flash program memory module. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? fcmen ieso clkouten boren<1:0> ? 38 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> config2 13:8 ? ? lvp debug lpbor borv stvren ? 40 7:0 ? ? ? vcapen (1) ? ?wrt<1:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by flash program memory.
? 2012 microchip technology inc. preliminary ds41624b-page 105 pic16(l)f1512/3 12.0 i/o ports each port has three standard registers for its operation. these registers are: ? trisx registers (data direction) ? portx registers (reads the levels on the pins of the device) ? latx registers (output latch) some ports may have one or more of the following additional registers. these registers are: ? anselx (analog select) ? wpux (weak pull-up) in general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. however, the pin can still be read. the data latch (latx registers) is useful for read-modify-write operations on the value that the i/o pins are driving. a write operation to the latx register has the same effect as a write to the corresponding portx register. a read of the latx register reads of the values held in the i/o port latches, while a read of the portx register reads the actual i/o pin value. ports that support analog inputs have an associated anselx register. when an ansel bit is set, the digital input buffer associated with that bit is disabled. disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 12-1 . figure 12-1: gene ric i/o port operation example 12-1: initializing porta table 12-1: port availability per device device porta portb portc porte pic16(l)f1512 pic16(l)f1513 q d ck write latx data register i/o pin read portx write portx trisx read latx data bus to peripherals anselx v dd v ss ; this code example illustrates ; initializing the porta register. the ; other ports are initialized in the same ; manner. banksel porta ; clrf porta ;init porta banksel lata ;data latch clrf lata ; banksel ansela ; clrf ansela ;digital i/o banksel trisa ; movlw b'00111000' ;set ra<5:3> as inputs movwf trisa ;and set ra<2:0> as ;outputs
pic16(l)f1512/3 ds41624b-page 106 preliminary ? 2012 microchip technology inc. 12.1 alternate pin function the alternate pin function control (apfcon) register is used to steer specific peripheral input and output functions between different pins. the apfcon register is shown in register 12-1 . for this device family, the following functions can be moved between different pins. ?ss (slave select) ? ccp2 these bits have no effect on the values of any tris register. port and tris overrides will be routed to the correct pin. the unselected pin will be unaffected. register 12-1: apfcon: alternate pin function co ntrol register u-0 u-0 u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 ? ? ? ? ? ? sssel ccp2sel bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-2 unimplemented: read as ? 0 ? bit 1 sssel: pin selection bit 0 =ss function is on ra5 1 =ss function is on ra0 bit 0 ccp2sel: pin selection bit 0 = ccp2 function is on rc1 1 = ccp2 function is on rb3
? 2012 microchip technology inc. preliminary ds41624b-page 107 pic16(l)f1512/3 12.2 porta registers porta is an 8-bit wide, bidirectional port. the corresponding data direction register is trisa ( register 12-3 ). setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., disable the output driver). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). example 12-1 shows how to initialize porta. reading the porta register ( register 12-2 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (lata). the trisa register ( register 12-3 ) controls the porta pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisa register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. 12.2.1 ansela register the ansela register ( register 12-5 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate ansela bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the ansela bits has no effect on digital output functions. a pin with tris clear and ansel set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 12.2.2 porta functions and output priorities each porta pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 12-2 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input functions, such as adc, are not shown in the priority lists. these inputs are active when the i/o pin is set for analog mode using the anselx registers. digital output functions may control the pin when it is in analog mode with the priority shown in table 12-2 . note: the ansela bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to ? 0 ? by user software. table 12-2: porta output priority pin name function priority (1) ra0 ra0 ra1 ra1 ra2 ra2 ra3 ra3 ra4 ra4 ra5 v cap (pic16f1512/3 only) ra5 ra6 clkout osc2 ra6 ra7 ra7 note 1: priority listed from highest to lowest.
pic16(l)f1512/3 ds41624b-page 108 preliminary ? 2012 microchip technology inc. register 12-2: porta: porta register r/w-x/x r/w-x/x r/w-x/x r/w-x/x r/w-x/x r/w-x/x r/w-x/x r/w-x/x ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 ra<7:0> : porta i/o value bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to porta are actually written to corresponding lata register. reads from porta register is return of actual i/o pin values. register 12-3: trisa: porta tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 trisa<7:0>: porta tri-state control bits 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output
? 2012 microchip technology inc. preliminary ds41624b-page 109 pic16(l)f1512/3 register 12-4: lata: porta data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lata7 lata6 lata5 lata4 lata3 lata2 lata1 lata0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 lata<7:0> : porta output latch value bits (1) note 1: writes to porta are actually written to corresponding lata register. reads from porta register is the return of actual i/o pin values. register 12-5: ansela: porta analog select register u-0 u-0 r/w-1/1 u-0 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 ? ? ansa5 ? ansa3 ansa2 ansa1 ansa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5 ansa5 : analog select between analog or digital function on pins ra5, respectively 0 = digital i/o. pin is assigned to port or digital special function. 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. bit 4 unimplemented: read as ? 0 ? bit 3-0 ansa<3:0> : analog select between analog or digital function on pins ra<3:0>, respectively 0 = digital i/o. pin is assigned to port or digital special function. 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin.
pic16(l)f1512/3 ds41624b-page 110 preliminary ? 2012 microchip technology inc. table 12-3: summary of regist ers associated with porta table 12-4: summary of conf iguration word with porta name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ?ansa5 ? ansa3 ansa2 ansa1 ansa0 109 apfcon ? ? ? ? ? ? sssel ccp2sel 106 lata lata7 lata6 lata5 lata4 lata3 lata2 lata1 lata0 109 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 165 porta ra7 ra6 ra5 ra4 ra3 ra2 ra1 ra0 108 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 108 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by porta. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? fcmen ieso clkouten boren<1:0.> ? 38 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by porta.
? 2012 microchip technology inc. preliminary ds41624b-page 111 pic16(l)f1512/3 12.3 portb registers portb is an 8-bit wide, bidirectional port. the corresponding data direction register is trisb ( register 12-7 ). setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 12-1 shows how to initialize an i/o port. reading the portb register ( register 12-6 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (latb). the trisb register ( register 12-7 ) controls the portb pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisb register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. 12.3.1 anselb register the anselb register ( register 12-9 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate anselb bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the anselb bits has no effect on digital output functions. a pin with tris clear and anselb set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 12.3.2 portb functions and output priorities each portb pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 12-5 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input and some digital input functions are not included in the list below. these input functions can remain active when the pin is configured as an output. certain digital input functions override other port functions and are included in tab le 1 2- 5 . note: the anselb bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to ? 0 ? by user software. table 12-5: portb output priority pin name function priority (1) rb0 rb0 rb1 rb1 rb2 rb2 rb3 ccp2 rb3 rb4 rb4 rb5 rb5 rb6 icdclk rb6 rb7 icddat rb7 note 1: priority listed from highest to lowest.
pic16(l)f1512/3 ds41624b-page 112 preliminary ? 2012 microchip technology inc. register 12-6: port b: portb register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 rb<7:0> : portb general purpose i/o pin bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to portb are actually written to corresponding latb register. reads from portb register is the return of actual i/o pin values. register 12-7: trisb: po rtb tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 trisb<7:0>: portb tri-state control bits 1 = portb pin configured as an input (tri-stated) 0 = portb pin configured as an output register 12-8: latb: portb data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 latb<7:0> : portb output latch value bits (1) note 1: writes to portb are actually written to corresponding latb register. reads from portb register is the return of actual i/o pin values.
? 2012 microchip technology inc. preliminary ds41624b-page 113 pic16(l)f1512/3 table 12-6: summary of regist ers associated with portb register 12-9: anselb: portb analog select register u-0 u-0 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 ansb<5:0> : analog select between analog or digital function on pins rb<5:0>, respectively 0 = digital i/o. pin is assigned to port or digital special function. 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. register 12-10: wpub: weak pull-up portb register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 wpub<7:0> : weak pull-up register bits 1 = pull-up enabled 0 = pull-up disabled note 1: global wpuen bit of the option_reg register must be cleared for individual pull-ups to be enabled. 2: the weak pull-up device is autom atically disabled if the pin is in configured as an output. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 113 apfcon ? ? ? ? ? ? sssel ccp2sel 106 latb latb7 latb6 latb5 latb4 latb3 latb2 latb1 latb0 112 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 165 portb rb7 rb6 rb5 rb4 rb3 rb2 rb1 rb0 112 trisb trisb7 trisb6 trisb5 tri sb4 trisb3 trisb2 trisb1 trisb0 112 wpub wpub7 wpub6 wpub5 wpub4 wpub3 wpub2 wpub1 wpub0 113 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by portb.
pic16(l)f1512/3 ds41624b-page 114 preliminary ? 2012 microchip technology inc. 12.4 portc registers portc is an 8-bit wide bidirectional port. the corresponding data direction register is trisc ( register 12-12 ). setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 12-1 shows how to initialize an i/o port. reading the portc register ( register 12-11 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (latc). the trisc register ( register 12-12 ) controls the portc pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisc register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. 12.4.1 anselc register the anselc register ( register 12-14 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate anselc bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the anselc bits has no effect on digital output functions. a pin with tris clear and anselc set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 12.4.2 portc functions and output priorities each portc pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 12-7 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input and some digital input functions are not included in the list below. these input functions can remain active when the pin is configured as an output. certain digital input functions override other port functions and are included in tab le 1 2- 7 . note: the anselc bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to ? 0 ? by user software. table 12-7: portc output priority pin name function priority (1) rc0 sosco rc0 rc1 sosci ccp2 rc1 rc2 ccp1 rc2 rc3 scl sck rc3 (2) rc4 sda rc4 (2) rc5 sdo rc5 rc6 ck tx rc6 rc7 dt rc7 note 1: priority listed from highest to lowest. 2: rc3 and rc4 read the i 2 c st input when i 2 c mode is enabled.
? 2012 microchip technology inc. preliminary ds41624b-page 115 pic16(l)f1512/3 register 12-11: portc: portc register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 rc<7:0> : portc general purpose i/o pin bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to portc are actually written to corresponding latc register. reads from portc register is the return of actual i/o pin values. register 12-12: trisc: po rtc tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 trisc<7:0>: portc tri-state control bits 1 = portc pin configured as an input (tri-stated) 0 = portc pin configured as an output register 12-13: latc: portc data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 latc<7:0> : portc output latch value bits (1) note 1: writes to portc are actually written to corresponding latc register. reads from portc register is the return of actual i/o pin values.
pic16(l)f1512/3 ds41624b-page 116 preliminary ? 2012 microchip technology inc. table 12-8: summary of regist ers associated with portc register 12-14: anselc: portc analog select register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 u-0 u-0 ansc7 ansc6 ansc3 ansc3 ansc3 ansc2 ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-2 ansc<7:0> : analog select between analog or digital function on pins rc<7:0>, respectively 0 = digital i/o. pin is assigned to port or digital special function. 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. bit 1-0 unimplemented: read as ? 0 ? note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselc ansc7 ansc6 ansc5 ansc4 ansc3 ansc2 ? ? 113 apfcon ? ? ? ? ? ? sssel ccp2sel 106 latc latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 112 portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 112 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 112 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by portc.
? 2012 microchip technology inc. preliminary ds41624b-page 117 pic16(l)f1512/3 12.5 porte registers porte is a 4-bit wide, bidirectional port. the corresponding data direction register is trise. setting a trise bit (= 1 ) will make the corresponding porte pin an input (i.e., put the corresponding output driver in a high-impedance mode). clearing a trise bit (= 0 ) will make the corresponding porte pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). the exception is re3, which is input only and its tris bit will always read as ? 1 ?. example 12-1 shows how to initialize an i/o port. reading the porte register ( register 12-15 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (late). re3 reads ? 0 ? when mclre = 1. 12.5.1 porte functions and output priorities porte has no peripheral outputs, so the porte output has no priority function.
pic16(l)f1512/3 ds41624b-page 118 preliminary ? 2012 microchip technology inc. register 12-15: porte: porte register u-0 u-0 u-0 u-0 r-x/x u-0 u-0 u-0 ? ? ? ? re3 ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented : read as ? 0 ? bit 3 re<3> : porte i/o value bit (re3 is read-only) bit 2-0 unimplemented : read as ? 0 ? register 12-16: trise: porte tri-state register u-0 u-0 u-0 u-0 u-1 u-0 u-0 u-0 ? ? ? ? ? (1) ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented : read as ? 0 ? bit 3 unimplemented : read as ? 1 ? bit 2-0 unimplemented : read as ? 0 ? note 1: unimplemented, read as ? 1 ?.
? 2012 microchip technology inc. preliminary ds41624b-page 119 pic16(l)f1512/3 table 12-9: summary of regist ers associated with porte table 12-10: summary of conf iguration word with porte register 12-17: wpue: weak pull-up porte register u-0 u-0 u-0 u-0 r/w-1/1 u-0 u-0 u-0 ? ? ? ? wpue3 ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented: read as ? 0 ? bit 3 wpue: weak pull-up register bit 1 = pull-up enabled 0 = pull-up disabled bit 2-0 unimplemented: read as ? 0 ? note 1: global wpuen bit of the option_reg register must be cleared for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is in configured as an output. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page a(a)dcon0 ? chs<4:0> go/done adon 153 ccpxcon ? ? dcxb<1:0> ccpxm<3:0> 246 porte ? ? ? ?re3 ? ? ? 118 trise ? ? ? ? ? (1) ? ? ? 118 wpue ? ? ? ? wpue3 ? ? ? 119 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by porte. note 1: unimplemented, read as ? 1 ?. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? fcmen ieso clkouten boren<1:0> ? 38 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by porte.
pic16(l)f1512/3 ds41624b-page 120 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds41624b-page 121 pic16(l)f1512/3 13.0 interrupt-on-change the portb pins can be configured to operate as interrupt-on-change (ioc) pins. an interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. any individual portb pin, or combination of portb pins, can be configured to generate an interrupt. the interrupt-on-change module has the following features: ? interrupt-on-change enable (master switch) ? individual pin configuration ? rising and falling edge detection ? individual pin interrupt flags figure 13-1 is a block diagram of the ioc module. 13.1 enabling the module to allow individual portb pins to generate an interrupt, the iocie bit of the intcon register must be set. if the iocie bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 13.2 individual pin configuration for each portb pin, a rising edge detector and a falling edge detector are present. to enable a pin to detect a rising edge, the associated iocbpx bit of the iocbp register is set. to enable a pin to detect a falling edge, the associated iocbnx bit of the iocbn register is set. a pin can be configured to detect rising and falling edges simultaneously by setting both the iocbpx bit and the iocbnx bit of the iocbp and iocbn registers, respectively. 13.3 interrupt flags the iocbfx bits located in the iocbf register are status flags that correspond to the interrupt-on-change pins of portb. if an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the iocie bit is set. the iocif bit of the intcon register reflects the status of all iocbfx bits. 13.4 clearing interrupt flags the individual status flags, (iocbfx bits), can be cleared by resetting them to zero. if another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. in order to ensure that no detected edge is lost while clearing flags, only and operations masking out known changed bits should be performed. the following sequence is an example of what should be performed. example 13-1: clearing interrupt flags (porta example) 13.5 operation in sleep the interrupt-on-change interrupt sequence will wake the device from sleep mode, if the iocie bit is set. if an edge is detected while in sleep mode, the iocbf register will be updated prior to the first instruction executed out of sleep. movlw 0xff xorwf iocaf, w andwf iocaf, f
pic16(l)f1512/3 ds41624b-page 122 preliminary ? 2012 microchip technology inc. figure 13-1: interrupt-on -change block diagram d ck r q d ck r q rbx iocbnx iocbpx q2 d ck s q q4q1 data bus = 0 or 1 write iocbfx iocie to data bus iocbfx edge detect ioc interrupt to cpu core from all other iocbfx individual pin detectors q1 q2 q3 q4 q4q1 q1 q2 q3 q4 q1 q2 q3 q4 q4 q4q1 q4q1 q4q1
? 2012 microchip technology inc. preliminary ds41624b-page 123 pic16(l)f1512/3 13.6 interrupt-on-change registers register 13-1: iocbp: interrupt-on-c hange portb positive edge register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 iocbp7 iocbp6 iocbp5 iocbp4 iocbp3 iocbp2 iocbp1 iocbp0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 iocbp<7:0>: interrupt-on-change portb positive edge enable bits 1 = interrupt-on-change enabled on the pin for a positive going edge. associated status bit and interrupt flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin. register 13-2: iocbn: interrupt-on-change portb negative edge register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 iocbn7 iocbn6 iocbn5 iocbn4 iocbn3 iocbn2 iocbn1 iocbn0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 iocbn<7:0>: interrupt-on-change portb negative edge enable bits 1 = interrupt-on-change enabled on the pin for a negative going edge. iocbfx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin. register 13-3: iocbf: interrupt- on-change portb flag register r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 iocbf7 iocbf6 iocbf5 iocbf4 iocbf3 iocbf2 iocbf1 iocbf0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hs - bit is set in hardware bit 7-0 iocbf7:0>: interrupt-on-change portb flag bits 1 = an enabled change was detected on the associated pin. set when iocbpx = 1 and a rising edge was detected on rbx, or when iocbnx = 1 and a falling edge was detected on rbx. 0 = no change was detected, or the user cleared the detected change.
pic16(l)f1512/3 ds41624b-page 124 preliminary ? 2012 microchip technology inc. table 13-1: summary of registers as sociated with interrupt-on-change name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 109 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 iocbf iocbp7 iocbp6 iocbp5 ioc bp4 iocbp3 iocbp2 iocbp1 iocbp0 123 iocbn iocbn7 iocbn6 iocbn5 iocbn4 iocbn3 iocbn2 iocbn1 iocbn0 123 iocbp iocbf7 iocbf6 iocbf5 iocbf4 iocbf3 iocbf2 iocbf1 iocbf0 123 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 108 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by interrupt-on-change.
? 2012 microchip technology inc. preliminary ds41624b-page 125 pic16(l)f1512/3 14.0 fixed voltage reference (fvr) the fixed voltage reference, or fvr, is a stable voltage reference, independent of v dd , with 1.024v, 2.048v or 4.096v selectable output levels. the output of the fvr can be configured to supply a reference voltage to the following: ? adc input channel ? adc positive reference ? comparator positive input the fvr can be enabled by setting the fvren bit of the fvrcon register. 14.1 independent gain amplifiers the output of the fvr supplied to the adc module is routed through a programmable gain amplifier. the amplifier can be configured to amplify the reference voltage by 1x, 2x or 4x, to produce the three possible voltage levels. the adfvr<1:0> bits of the fvrcon register are used to enable and configure the gain amplifier settings for the reference supplied to the adc module. refer- ence section 16.0 ?analog-to-digital converter (adc) module? for additional information. 14.2 fvr stabilization period when the fixed voltage reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. once the circuits stabilize and are ready for use, the fvrrdy bit of the fvrcon register will be set. see section 25.0 ?electrical specifications? for the minimum delay requirement. figure 14-1: voltage reference block diagram fvr buffer1 (to adc module) x1 x2 x4 + - 1.024v fixed reference fvren fvrrdy 2 adfvr<1:0> any peripheral requiring the fixed reference (see table 14-1 ) table 14-1: peripherals requiring the fixed voltage reference (fvr) peripheral conditions description hfintosc fosc<2:0> = 100 and ircf<3:0> = 000x intosc is active and device is not in sleep bor boren<1:0> = 11 bor always enabled boren<1:0> = 10 and borfs = 1 bor disabled in sleep mode, bor fast start enabled. boren<1:0> = 01 and borfs = 1 bor under software control, bor fast start enabled ldo all pic16f151x devices, when vregpm = 1 and not in sleep the device runs off of the low-power regulator when in sleep mode.
pic16(l)f1512/3 ds41624b-page 126 preliminary ? 2012 microchip technology inc. 14.3 fvr control registers table 14-2: summary of registers associated with the fixed voltage reference register 14-1: fvrcon: fixed voltage reference control register r/w-0/0 r-q/q r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 fvren fvrrdy (1) tsen tsrng ? ?adfvr<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 fvren: fixed voltage reference enable bit 0 = fixed voltage reference is disabled 1 = fixed voltage reference is enabled bit 6 fvrrdy: fixed voltage reference ready flag bit (1) 0 = fixed voltage reference output is not ready or not enabled 1 = fixed voltage reference output is ready for use bit 5 tsen: temperature indicator enable bit 0 = temperature indicator is disabled 1 = temperature indicator is enabled bit 4 tsrng: temperature indicator range selection bit 0 =v out = v dd - 2v t (low range) 1 =v out = v dd - 4v t (high range) bit 3-2 unimplemented: read as ? 0 ? bit 1-0 adfvr<1:0>: adc fixed voltage reference selection bits 00 = adc fixed voltage reference peripheral output is off 01 = adc fixed voltage reference peripheral output is 1x (1.024v) 10 = adc fixed voltage reference peripheral output is 2x (2.048v) (2) 11 = adc fixed voltage reference peripheral output is 4x (4.096v) (2) note 1: fvrrdy is always ? 1 ? on pic16f151x only. 2: fixed voltage reference output cannot exceed v dd . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page fvrcon fvren fvrrdy tsen tsrng ? ?adfvr<1:0> 126 legend: shaded cells are unused by the fixed voltage reference module.
? 2012 microchip technology inc. preliminary ds41624b-page 127 pic16(l)f1512/3 15.0 temperature indicator module this family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. the circuit?s range of operating temperature falls between -40c and +85c. the output is a voltage that is proportional to the device temperature. the output of the temperature indicator is internally connected to the device adc. the circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. a one- point calibration allows the circuit to indicate a temperature closely surrounding that point. a two-point calibration allows the circuit to sense the entire range of temperature more accurately. reference application note an1333, ? use and calibration of the internal temperature indicator ? (ds01333) for more details regarding the calibration process. 15.1 circuit operation figure 15-1 shows a simplified block diagram of the temperature circuit. the proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. equation 15-1 describes the output characteristics of the temperature indicator. equation 15-1: v out ranges the temperature sense circuit is integrated with the fixed voltage reference (fvr) module. see section 14.0 ?fixed voltage reference (fvr)? for more information. the circuit is enabled by setting the tsen bit of the fvrcon register. when disabled, the circuit draws no current. the circuit operates in either high or low range. the high range, selected by setting the tsrng bit of the fvrcon register, provides a wider output voltage. this provides more resolution over the temperature range, but may be less consistent from part to part. this range requires a higher bias voltage to operate and thus, a higher v dd is needed. the low range is selected by clearing the tsrng bit of the fvrcon register. the low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. the low range is provided for low voltage operation. figure 15-1: temperature circuit diagram 15.2 minimum operating v dd when the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. when the temperature circuit is operated in high range, the device operating voltage, v dd , must be high enough to ensure that the temperature circuit is correctly biased. table 15-1 shows the recommended minimum v dd vs. range setting. table 15-1: recommended v dd vs. range 15.3 temperature output the output of the circuit is measured using the internal analog-to-digital converter. a channel is reserved for the temperature circuit output. refer to section 16.0 ?analog-to-digital converter (adc) module? for detailed information. high range: v out = v dd - 4v t low range: v out = v dd - 2v t min. v dd , tsrng = 1 min. v dd , tsrng = 0 3.6v 1.8v tsen adc mux tsrng v dd adc chs bits (adcon0 register) n v out
pic16(l)f1512/3 ds41624b-page 128 preliminary ? 2012 microchip technology inc. 15.4 adc acquisition time to ensure accurate temperature measurements, the user must wait at least 200 ? s after the adc input multiplexer is connected to the temperature indicator output before the conversion is performed. in addition, the user must wait 200 ? s between sequential conversions of the temperature indicator output. table 15-2: summary of registers associated with the temperature indicator name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page fvrcon fvren fvrrdy tsen tsrng ? ? adfvr<1:0> 126 legend: shaded cells are unused by the temperature indicator module.
? 2012 microchip technology inc. preliminary ds41624b-page 129 pic16(l)f1512/3 16.0 analog-to-digital converter (adc) module the analog-to-digital converter (adc) allows conversion of an analog input signal to a 10-bit binary representation of that signal. this device uses analog inputs, which are multiplexed into a single sample and hold circuit. the output of the sample and hold is connected to the input of the converter. the converter generates a 10-bit binary result via successive approximation and stores the conversion result into the adc result registers (adresh:adresl register pair). figure 16-1 shows the block diagram of the adc. the adc voltage reference is software selectable to be either internally generated or externally supplied. the adc can generate an interrupt upon completion of a conversion. this interrupt can be used to wake-up the device from sleep. note: this section of the adc chapter discusses legacy operation. if new capacitive voltage divider (cvd) features are needed, refer to section 16.5 ?capacitive voltage divider (cvd)? for more information.
pic16(l)f1512/3 ds41624b-page 130 preliminary ? 2012 microchip technology inc. figure 16-1: adc block diagram note 1: when adon = 0 , all multiplexer inputs are disconnected. 2: see aadcon0 register ( register 16-7 ) for detailed analog channel selection per device. 3: adres0h and aadres0h are the same register in two locations, bank 1 and bank 14. see table 3-9 . 4: adres0l and aadres0l are the same register in two locations, bank 1 and bank 14. see ta b l e 3 - 9 . v dd v ref + adpref = 10 adpref = 0x fvr fvr buffer1 adon (1) go/done v ss adc 00000 00001 00010 00011 chs<4:0> (2) an0 an1 an2 v ref +/an3 11111 adresxl (4) 10 16 adfm 0 = left justify 1 = right justify temp indicator 11101 10011 an19 11001 reserved adpref = 11 an4 reserved reserved reserved an8 00100 00101 00110 00111 01000 10100 reserved 11010 vrefh (adc positive reference) 11011 vrefl (adc negative reference) adresxh (3) an9 01001 an10 01010 an11 01011 an12 01100 an13 01101 an14 01110 an15 01111 an16 10000 an17 10001 an18 10010 11100 reserved 11110 reserved
? 2012 microchip technology inc. preliminary ds41624b-page 131 pic16(l)f1512/3 16.1 adc configuration when configuring and using the adc the following functions must be considered: ? port configuration ? channel selection ? adc voltage reference selection ? adc conversion clock source ? interrupt control ? result formatting 16.1.1 port configuration the adc can be used to convert both analog and digital signals. when converting analog signals, the i/o pin should be configured for analog by setting the associated tris and ansel bits. refer to section 12.0 ?i/o ports? for more information. 16.1.2 channel selection there are up to 21 channel selections available: - an<19:8, 4:0> pins - v ref + (adc positive reference) - v ref - (adc negative reference) - temperature indicator - fvr (fixed voltage reference) output refer to section 14.0 ?fixed voltage reference (fvr)? and section 15.0 ?temperature indicator module? for more information on these channel selections. the chs bits of the adcon0 register determine which channel is connected to the sample and hold circuit. when changing channels, a delay is required before starting the next conversion. refer to section 16.6 ?automated capacitive voltage divider? for more information. 16.1.3 adc voltage reference the adpref bits of the adcon1 register provides control of the positive voltage reference. the positive voltage reference can be: ?v ref + pin ?v dd ? fvr (fixed voltage reference) see section 14.0 ?fixed voltage reference (fvr)? for more details on the fixed voltage reference. 16.1.4 conversion clock the source of the conversion clock is software selectable via the adcs bits of the adcon1 register. there are seven possible clock options: ?f osc /2 ?f osc /4 ?f osc /8 ?f osc /16 ?f osc /32 ?f osc /64 ?f rc (dedicated internal oscillator) the time to complete one bit conversion is defined as t ad . one full 10-bit conversion requires 11.5 t ad periods as shown in figure 16-2 . for correct conversion, the appropriate t ad specifica- tion must be met. refer to the a/d conversion require- ments in section 25.0 ?electrical specifications? for more information. table 16-5 gives examples of appropriate adc clock selections. note: analog voltages on any pin that is defined as a digital input may cause the input buf- fer to conduct excess current. note: unless using the f rc , any changes in the system clock frequency will change the adc clock frequency, which may adversely affect the adc result.
pic16(l)f1512/3 ds41624b-page 132 preliminary ? 2012 microchip technology inc. table 16-1: adc clock period (t ad ) v s . device operating frequencies figure 16-2: analog-to-dig ital conversion t ad cycles adc clock period (t ad ) device frequency (f osc ) adc clock source adcs<2:0> 20 mhz 16 mhz 8 mhz 4 mhz 1 mhz fosc/2 000 100 ns (2) 125 ns (2) 250 ns (2) 500 ns (2) 2.0 ? s fosc/4 100 200 ns (2) 250 ns (2) 500 ns (2) 1.0 ? s4.0 ? s fosc/8 001 400 ns (2) 0.5 ? s (2) 1.0 ? s2.0 ? s 8.0 ? s (3) fosc/16 101 800 ns 1.0 ? s2.0 ? s4.0 ? s 16.0 ? s (3) fosc/32 010 1.6 ? s2.0 ? s4.0 ? s 8.0 ? s (3) 32.0 ? s (3) fosc/64 110 3.2 ? s4.0 ? s 8.0 ? s (3) 16.0 ? s (3) 64.0 ? s (3) f rc x11 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) legend: shaded cells are outside of recommended range. note 1: the f rc source has a typical t ad time of 1.6 ? s for v dd . 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: the adc clock period (t ad ) and total adc conversion time can be minimized when the adc clock is derived from the system clock f osc . however, the f rc clock source must be used when conversions are to be performed with the device in sleep mode. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go bit holding capacitor is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy - t ad adresh:adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is connected to analog input. conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 on the following cycle:
? 2012 microchip technology inc. preliminary ds41624b-page 133 pic16(l)f1512/3 16.1.5 interrupts the adc module allows for the ability to generate an interrupt upon completion of an analog-to-digital conversion. the adc interrupt flag is the adif bit in the pir1 register. the adc interrupt enable is the adie bit in the pie1 register. the adif bit must be cleared in software. this interrupt can be generated while the device is operating or while in sleep. if the device is in sleep, the interrupt will wake-up the device. upon waking from sleep, the next instruction following the sleep instruction is always executed. if the user is attempting to wake-up from sleep and resume in-line code execution, the gie and peie bits of the intcon register must be disabled. if the gie and peie bits of the intcon register are enabled, execution will switch to the interrupt service routine. 16.1.6 result formatting the 10-bit a/d conversion result can be supplied in two formats, left justified or right justified. the adfm bit of the adcon1 register controls the output format. figure 16-7 shows the two output formats. figure 16-3: 10-bit a/d conv ersion result format note 1: the adif bit is set at the completion of every conversion, regardless of whether or not the adc interrupt is enabled. 2: the adc operates during sleep only when the f rc oscillator is selected. adresh adresl (adfm = 0 )msb lsb bit 7 bit 0 bit 7 bit 0 10-bit a/d result unimplemented: read as ? 0 ? (adfm = 1 ) msb lsb bit 7 bit 0 bit 7 bit 0 unimplemented: read as ? 0 ? 10-bit a/d result
pic16(l)f1512/3 ds41624b-page 134 preliminary ? 2012 microchip technology inc. 16.2 adc operation 16.2.1 starting a conversion to enable the adc module, the adon bit of the adcon0 register must be set to a ? 1 ?. setting the go/ done bit of the adcon0 register to a ? 1 ? will start the analog-to-digital conversion. 16.2.2 completion of a conversion when the conversion is complete, the adc module will: ? clear the go/done bit ? set the adif interrupt flag bit ? update the adresh and adresl registers with new conversion result 16.2.3 terminating a conversion if a conversion must be terminated before completion, the go/done bit can be cleared in software. the adresh and adresl registers will be updated with the partially complete analog-to-digital conversion sample. incomplete bits will match the last bit converted. 16.2.4 adc operation during sleep the adc module can operate during sleep. this requires the adc clock source to be set to the f rc option. when the f rc clock source is selected, the adc waits one additional instruction before starting the conversion. this allows the sleep instruction to be executed, which can reduce system noise during the conversion. if the adc interrupt is enabled, the device will wake-up from sleep when the conversion completes. if the adc interrupt is disabled, the adc module is turned off after the conversion completes, although the adon bit remains set. when the adc clock source is something other than f rc , a sleep instruction causes the present conversion to be aborted and the adc module is turned off, although the adon bit remains set. 16.2.5 special event trigger the special event trigger allows periodic adc measurements without software intervention, using the trigsel bits of the aadcon2 register. when this trigger occurs, the go/done bit is set by hardware from one of the following sources: ? ccp1 ? ccp2 ? timer0 overflow ? timer1 overflow ? timer2 match to pr2 using the special event trigger does not assure proper adc timing. it is the user?s responsibility to ensure that the adc timing requirements are met. refer to section 21.0 ?capture/compare/pwm modules? , section 17.0 ?timer0 module? , section 18.0 ?timer1 module with gate control? , and section 19.0 ?timer2 module? for more information. note: the go/done bit should not be set in the same instruction that turns on the adc. refer to section 16.2.6 ?a/d conver- sion procedure? . note: a device reset forces all registers to their reset state. thus, the adc module is turned off and any pending conversion is terminated. table 16-2: special event trigger device source pic16(l)f1512/3 ccp1, ccp2, tmr0, tmr1, tmr2
? 2012 microchip technology inc. preliminary ds41624b-page 135 pic16(l)f1512/3 16.2.6 a/d conversion procedure this is an example procedure for using the adc to perform an analog-to-digital conversion: 1. configure port: ? disable pin output driver (refer to the tris register) ? configure pin as analog (refer to the ansel register) 2. configure the adc module: ? select adc conversion clock ? configure voltage reference ? select adc input channel ? turn on adc module 3. configure adc interrupt (optional): ? clear adc interrupt flag ? enable adc interrupt ? enable peripheral interrupt ? enable global interrupt (1) 4. wait the required acquisition time (2) . 5. start conversion by setting the go/done bit. 6. wait for adc conversion to complete by one of the following: ? polling the go/done bit ? waiting for the adc interrupt (interrupts enabled) 7. read adc result in adres0h and adres0l. 8. clear the adc interrupt flag (required if interrupt is enabled). example 16-1: a/d conversion note 1: the global interrupt can be disabled if the user is attempting to wake-up from sleep and resume in-line code execution. 2: refer to section 16.4 ?a/d acquisition requirements? . ;this code block configures the adc ;for polling, vdd and vss references, frc ;clock and an0 input. ; ;conversion start & polling for completion ; are included. ; banksel adcon1 ; movlw b?11110000? ;right justify, frc ;clock movwf adcon1 ;vdd and vss vref banksel trisa ; bsf trisa,0 ;set ra0 to input banksel ansel ; bsf ansel,0 ;set ra0 to analog banksel adcon0 ; movlw b?00000001? ;select channel an0 movwf adcon0 ;turn adc on call sampletime ;acquisiton delay bsf adcon0,adgo ;start conversion btfsc adcon0,adgo ;is conversion done? goto $-1 ;no, test again banksel adresh ; movf adresh,w ;read upper 2 bits movwf resulthi ;store in gpr space banksel adresl ; movf adresl,w ;read lower 8 bits movwf resultlo ;store in gpr space
pic16(l)f1512/3 ds41624b-page 136 preliminary ? 2012 microchip technology inc. 16.3 adc register definitions the following registers are used to control the operation of the adc. register 16-1: adcon0: a/ d control register 0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? chs<4:0> go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-2 chs<4:0>: analog channel select bits 11111 = fvr (fixed voltage reference) buffer 1 output (1) 11110 = reserved. no channel connected. 11101 = temperature indicator (2) . 11100 = reserved. no channel connected. 11011 =v refl (adc negative reference) 11010 =v refh (adc positive reference) (3) 11001 = reserved. no channel connected. ? ? ? 10100 = reserved. no channel connected. 10011 =an19 10010 =an18 10001 =an17 10000 =an16 01111 =an15 01110 =an14 01101 =an13 01100 =an12 01011 =an11 01010 =an10 01001 =an9 01000 =an8 00111 = reserved. no channel connected. 00110 = reserved. no channel connected. 00101 = reserved. no channel connected. 00100 =an4 00011 =an3 00010 =an2 00001 =an1 00000 =an0 bit 1 go/done : a/d conversion status bit 1 = a/d conversion cycle in progress. setting this bit starts an a/d conversion cycle. this bit is automatically cleared by hardware when the a/d conversion has completed. 0 = a/d conversion completed/not in progress bit 0 adon: adc enable bit 1 = adc is enabled 0 = adc is disabled and consumes no operating current note 1: see section 14.0 ?fixed voltage reference (fvr)? for more information. 2: see section 15.0 ?temperature indicator module? for more information. 3: conversion results for the v refh selection may contain errors due to noise.
? 2012 microchip technology inc. preliminary ds41624b-page 137 pic16(l)f1512/3 register 16-2: adcon1: a/ d control register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 adfm adcs<2:0> ? ? adpref<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 adfm: a/d result format select bit 1 = right justified. six most significant bits of adresh are set to ? 0 ? when the conversion result is loaded. 0 = left justified. six least significant bits of adresl are set to ? 0 ? when the conversion result is loaded. bit 6-4 adcs<2:0>: a/d conversion clock select bits 000 =f osc /2 001 =f osc /8 010 =f osc /32 011 =f rc (clock supplied from a dedicated rc oscillator) 100 =f osc /4 101 =f osc /16 110 =f osc /64 111 =f rc (clock supplied from a dedicated rc oscillator) bit 3-2 unimplemented: read as ? 0 ? bit 1-0 adpref<1:0>: a/d positive voltage reference configuration bits 00 =v ref is connected to v dd 01 = reserved 10 =v ref is connected to external v ref + pin (1) 11 =v ref is connected to internal fixed voltage reference (fvr) module (1) note 1: when selecting the fvr or the v ref + pin as the source of the positive reference, be aware that a minimum voltage specification exists. see section 25.0 ?electrical specifications? for details.
pic16(l)f1512/3 ds41624b-page 138 preliminary ? 2012 microchip technology inc. register 16-3: adres0h: adc result register high (adresh) adfm = 0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<9:2> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 adres<9:2> : adc result register bits upper 8 bits of 10-bit conversion result register 16-4: adres0l: adc result register low (adresl) adfm = 0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<1:0> ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 adres<1:0> : adc result register bits lower 2 bits of 10-bit conversion result bit 5-0 reserved : do not use.
? 2012 microchip technology inc. preliminary ds41624b-page 139 pic16(l)f1512/3 register 16-5: adres0h: adc result register high (adresh) adfm = 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u ? ? ? ? ? ? adres<9:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-2 reserved : do not use. bit 1-0 adres<9:8> : adc result register bits upper 2 bits of 10-bit conversion result register 16-6: adres0l: adc result register low (adresl) adfm = 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 adres<7:0> : adc result register bits lower 8 bits of 10-bit conversion result
pic16(l)f1512/3 ds41624b-page 140 preliminary ? 2012 microchip technology inc. 16.4 a/d acquisition requirements for the adc to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 16-4 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), refer to figure 16-4 . the maximum recommended impedance for analog sources is 10 k ? . as the source impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (or changed), an a/d acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 16-1 may be used. this equation assumes that 1/2 lsb error is used (1,024 steps for the adc). the 1/2 lsb error is the maximum error allowed for the adc to meet its specified resolution. equation 16-1: acquisition time example t acq amplifier settling time hold capacitor charging time temperature coefficient ++ = t amp t c t coff ++ = 2s t c temperature - 25c ?? 0.05s/c ?? ?? ++ = t c c hold r ic r ss r s ++ ?? ln(1/2047) ? = 10pf 1k ? 7k ? 10k ? ++ ?? ? ln(0.000488) = 1.37 = s v applied 1e tc ? rc --------- ? ?? ?? ?? v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? = v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? v chold = v applied 1e t c ? rc --------- - ? ?? ?? ?? v chold = ;[1] v chold charged to within 1/2 lsb ;[2] v chold charge response to v applied ;combining [1] and [2] the value for t c can be approximated with the following equations: solving for t c : therefore: temperature 50c and external impedance of 10k ? 5.0v v dd = assumptions: note: where n = number of bits of the adc. t acq 2s 1.37 s 50c- 25c ?? 0.05 s/c ?? ?? ++ = 4.62s = note 1: the reference voltage (v ref ) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specification.
? 2012 microchip technology inc. preliminary ds41624b-page 141 pic16(l)f1512/3 figure 16-4: analog input model figure 16-5: adc transfer function c pin va rs analog 5 pf v dd v t ? 0.6v v t ? 0.6v i leakage (1) r ic ? 1k sampling switch ss rss c hold = 10 pf v ss /v ref - 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance various junctions r ss note 1: refer to section 25.0 ?electrical specifications? . r ss = resistance of sampling switch input pin 3ffh 3feh adc output code 3fdh 3fch 03h 02h 01h 00h full-scale 3fbh 0.5 lsb v ref - zero-scale transition v ref + transition 1.5 lsb full-scale range analog input voltage
pic16(l)f1512/3 ds41624b-page 142 preliminary ? 2012 microchip technology inc. table 16-3: summary of registers associated with adc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page adcon0 ? chs<4:0> go/done adon 153 adcon1 adfm adcs<2:0> ? ? adpref<1:0> 154 adres0h a/d result register high 160 , 139 adres0l a/d result register low 160 , 139 ansela ? ?ansa5 ?ansa3 ansa2 ansa1 ansa0 109 anselb ? ?ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 113 anselc ansc7 ansc6 ansc5 ansc4 ansc3 ansc2 ? ? 116 ccp1con ? ? dc1b<1:0> ccp1m<3:0> 246 ccp2con ? ? dc2b<1:0> ccp2m<3:0> 246 fvrcon fvren fvrrdy tsen tsrng ? ?adfvr<1:0> 126 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 108 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 112 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 115 legend: ? = unimplemented read as ? 0 ?. shaded cells are not used for adc module.
? 2012 microchip technology inc. preliminary ds41624b-page 143 pic16(l)f1512/3 16.5 capacitive voltage divider (cvd) 16.5.1 adc register mapping the adc module with capacitive voltage divider (cvd) is an enhanced version of the standard adc module as stated in section 16.0 ?analog-to-digital converter (adc) module? through section 16.3 ?adc register definitions? and is backward compatible with the other devices in this family. control of the standard adc module uses bank 1 registers, see table 16-4 . this set of registers are mapped into bank 14 with the control registers for the adc module with capacitive voltage divider control. although this subset of registers have different names, they are identical. since the registers for the standard adc are mapped into the bank 14 address space, any changes to registers in bank 1 will be reflected in bank 14 and vice-versa. table 16-4: adc register mapping 16.5.2 conversion clock the source of the conversion clock is software selectable via the adcs bits of the aadcon1 register. there are seven possible clock options: ?f osc /2 ?f osc /4 ?f osc /8 ?f osc /16 ?f osc /32 ?f osc /64 ?f rc (dedicated internal oscillator) the time to complete one bit conversion is defined as t ad . one full 10-bit conversion requires 11.5 t ad periods as shown in figure 16-6 . for correct conversion, the appropriate t ad specifica- tion must be met. refer to the a/d conversion require- ments in section 25.0 ?electrical specifications? for more information. table 16-5 gives examples of appropriate adc clock selections. [bank 14 address] [bank 1 address] adc with capacitive voltage divider adc [711h] aadcon0 (1) [09dh] adcon0 (1) [712h] aadcon1 (1) [09eh] adcon1 (1) [713h] aadcon2 [714h] aadcon3 [715h] aadstat [716h] aadpre [717h] aadacq [718h] aadgrd [719h] aadcap [71ah] aadres0l (1) [09bh] adres0l (1) [71bh] aadres0h (1) [09ch] adres0h (1) [71ch] aadres1l [71dh] aadres1l note 1: register is mapped in bank 1 and bank 14, using different names in each bank. note: unless using the f rc , any changes in the system clock frequency will change the adc clock frequency, which may adversely affect the adc result.
pic16(l)f1512/3 ds41624b-page 144 preliminary ? 2012 microchip technology inc. table 16-5: adc clock period (t ad ) v s . device operating frequencies figure 16-6: analog-to-digit al single conversion (addsen = 0 ) t ad cycles adc clock period (t ad ) device frequency (f osc ) adc clock source adcs<2:0> 20 mhz 16 mhz 8 mhz 4 mhz 1 mhz fosc/2 000 100 ns (2) 125 ns (2) 250 ns (2) 500 ns (2) 2.0 ? s fosc/4 100 200 ns (2) 250 ns (2) 500 ns (2) 1.0 ? s4.0 ? s fosc/8 001 400 ns (2) 0.5 ? s (2) 1.0 ? s2.0 ? s 8.0 ? s (3) fosc/16 101 800 ns 1.0 ? s2.0 ? s4.0 ? s 16.0 ? s (3) fosc/32 010 1.6 ? s2.0 ? s4.0 ? s 8.0 ? s (3) 32.0 ? s (3) fosc/64 110 3.2 ? s4.0 ? s 8.0 ? s (3) 16.0 ? s (3) 64.0 ? s (3) f rc x11 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) 1.0-6.0 ? s (1,4) legend: shaded cells are outside of recommended range. note 1: the f rc source has a typical t ad time of 1.6 ? s for v dd . 2: these values violate the minimum required t ad time. 3: for faster conversion times, the selection of another clock source is recommended. 4: the adc clock period (t ad ) and total adc conversion time can be minimized when the adc clock is derived from the system clock f osc . however, the f rc clock source must be used when conversions are to be performed with the device in sleep mode. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 11 set go/done bit holding capacitor c hold is disconnected from analog input (typically 100 ns) t ad 9 t ad 10 t cy - t ad aadres0h:aadres0l is loaded, adif bit is set, conversion starts b0 b9 b6 b5 b4 b3 b2 b1 b8 b7 on the following cycle: 1-127 t inst 1-127 t inst pre-charge acquisition/ sharing time time conversion time if adpre = 0 if adacq = 0 if adpre = 0 if adacq = 0 go/done bit is cleared (traditional timing of adc conversion) external and internal channels are charged/discharged external and internal channels share charge (traditional operation start) (t pre ) (t acq )
? 2012 microchip technology inc. preliminary ds41624b-page 145 pic16(l)f1512/3 16.5.3 result formatting the 10-bit a/d conversion result can be supplied in two formats, left justified or right justified. the adfm bit of the aadcon1 register controls the output format. figure 16-7 shows the two output formats. figure 16-7: 10-bit a/d conv ersion result format aadres0h aadres0l (adfm = 0 )msb lsb bit 7 bit 0 bit 7 bit 0 10-bit a/d result unimplemented: read as ? 0 ? (adfm = 1 ) msb lsb bit 7 bit 0 bit 7 bit 0 unimplemented: read as ? 0 ? 10-bit a/d result
pic16(l)f1512/3 ds41624b-page 146 preliminary ? 2012 microchip technology inc. 16.6 automated capacitive voltage divider 16.6.1 conversion sequence the conversion sequence can be expanded into three stages; pre-charge time, acquisition time, and conversion. see figure 16-6 for basic information on the timing of these stages. 16.6.2 pre-charge timer the pre-charge stage is an optional 1-127 instruction cycle time used to put the external adc channel and the internal sample and hold capacitor (c hold ) into preconditioned states. the pre-charge stage of conversion is enabled by writing a non-zero value to the adpre<6:0> bits of the aadpre register. this stage is initiated when a conversion sequence is started by either the go/done bit or a special event trigger. when initiating an adc conversion, if the adpre bits are cleared, this stage is skipped. during the pre-charge time, c hold is shorted to either v dd or v ss , depending on the value of the adippol bit of the aadcon3 register. the port pin logic of the selected analog channel is overridden to drive a digital high or low out. the output polarity of this override is determined by the adeppol bit of the aadcon3 register. when the adooen bit of the aadcon3 register is set, then the adout pin is overridden during pre-charge. this override functions the same as the channel pin overrides, but the polarity is selected by the adippol bit. even though the analog channel of the pin is selected, the analog multiplexer is forced open during the pre- charge stage. the adc multiplexor logic is overridden and disabled only during the pre-charge time. 16.6.3 acquisition timer the acquisition time is used to either acquire the signal or to charge share. the acquisition time counts from 1 to 127 instruction cycle times and is used to allow the voltage on the internal sample and hold capacitor (c hold ) to charge or discharge from the selected analog channel. the acquisition time of conversion is enabled by writing a non-zero value to the adacq<6:0> bits of the aadacq register. when the acquisition time is enabled, the time starts immediately follow the pre-charge stage. otherwise, the acquisition time is initiated by either setting the go/done bit or a special event trigger. at the start of the acquisition stage, the selected adc channel is connected to c hold . this allows charge sharing between the pre-charged channel and the c hold capacitor. see figure 16-6 . 16.6.4 starting a conversion to enable the adc module, the adon bit of the aadcon0 register must be set to a ? 1 ?. setting the go/ done bit of the aadcon0 register to a ? 1 ? in software or by the special event trigger inputs, will start the analog-to-digital conversion. once a conversion begins, it proceeds until complete, while adon is set. if adon is cleared (disabled by software), the conversion is halted. the go/done status bit of the aadcon0 register indicates that a conversion is occurring, regardless of the starting trigger. see figure 16-6 . 16.6.5 completion of a conversion when the conversion is complete, the adc module will: ? clear the go/done bit ? set the adif interrupt flag bit ? update the aadresxh and aadresxl registers with new conversion result 16.6.6 terminating a conversion if a conversion must be terminated before completion, the go/done bit can be cleared in software. the aadresxh and aadresxl registers will be updated with the partially complete analog-to-digital conversion sample. incomplete bits will match the last bit converted. 16.6.7 double sample conversion double sampling can be enabled by the addsen bit of the aadcon3 register. when this bit is set, two conversions are completed by each initiation of the go/ done bit or a special event trigger. the go/done bit stays set for the duration of both conversions and can be used to cancel a conversion early. the first conversion is written to the aadres0h and aadres0l registers. the second conversion starts two clock cycles after the first has completed and the go/done bit remains set. when the adipen bit of aadcon3 is set, the value used by the adc for the adeppol, adippol, and grdpol bits is inverted. the value stored in those bit locations is unchanged. all other control signals remain unchanged from the first conversion. the result of the second conversion is stored in the aadres1h and aadres1l registers. see figure 16-8 , figure 16-9 and figure 16-10 for more information. note: the go/done bit should not be set in the same instruction that turns on the adc. refer to section 16.6.11 ?a/d double conversion procedure? . note: a device reset forces all registers to their reset state. thus, the adc module is turned off and any pending conversion is terminated.
pic16(l)f1512/3 ds41624b-page 147 preliminary ? 2012 microchip technology inc. figure 16-8: double sa mple conversion sequence (addsen = 1 , adipen = 1 , guard-ring, grdpol = 1 ) 9th 8th 7th 6th 5th 4th 3rd 2nd 1st second result 1-127 t inst t ad conversion clock aadresxl/h<9:0> note 1: when conversion clock is adcrc, pre-charge and acquisition timers are clocked by adcrc. 10?h000 written to 9th 8th 7th 6th 5th 4th 3rd 2nd 1st 10?h000 first result ready pre-charge aadpre[6:0] acquisition aadacq[6:0] pre-charge aadpre[6:0] acquisition aadacq[6:0] aadres1l/h first result written to aadres0l/h anx digital ?1? out digital ?0? out go/done 1-127 t inst 1-127 t inst 1-127 t inst t pre t acq t conv (1) (1) (1) (1) 2 inst t pre t acq t conv adstat[2:0] 3?b001 3?b010 3?b011 3?b101 3?b110 3?b111 3?b000 analog input trisx control analog input trisx control adgrda adgrdb guard a and b initialized guard a and b initialized (adeppol = 1 ) chold (adippol = 0 ) shorted to v refl hold during conversion shorted to v refh hold during conversion charge sharing charge sharing
? 2012 microchip technology inc. preliminary ds41624b-page 148 pic16(l)f1512/3 figure 16-9: double sa mple conversion sequence (addsen = 1 , adipen = 1 , adooen = 1 ) 9th 8th 7th 6th 5th 4th 3rd 2nd 1st second result 1-127 t inst t ad conversion clock aadresxl/h<9:0> note 1: when conversion clock is adcrc, pre-charge and acquisition timers are clocked by adcrc. 10?h000 written to 9th 8th 7th 6th 5th 4th 3rd 2nd 1st 10?h000 first result ready pre-charge aadpre[6:0] acquisition aadacq[6:0] pre-charge aadpre[6:0] acquisition aadacq[6:0] aadres1l/h first result written to aadres0l/h anx digital ?1? out digital ?0? out go/done 1-127 t inst 1-127 t inst 1-127 t inst t pre t acq t conv (1) (1) (1) (1) 2 inst t pre t acq t conv adstat[2:0] 3?b001 3?b010 3?b011 3?b101 3?b110 3?b111 3?b000 analog input trisx control analog input trisx control adout (adeppol = 1 ) digital ?0? out trisx control digital ?1? out trisx control (adoen = 1 ) chold (adippol = 0 ) shorted to v refl hold during conversion shorted to v refh hold during conversion charge sharing charge sharing
pic16(l)f1512/3 ds41624b-page 149 preliminary ? 2012 microchip technology inc. figure 16-10: double sample co nversion sequence (addsen = 1 , adipen = 0 , guard-ring and grdpol = 1 ) 9th 8th 7th 6th 5th 4th 3rd 2nd 1st second result 1-127 t inst t ad conversion clock aadresxl/h<9:0> note 1: when conversion clock is adcrc, pre-charge and acquisition timers are clocked by adcrc. 10?h000 written to 9th 8th 7th 6th 5th 4th 3rd 2nd 1st 10?h000 first result ready pre-charge aadpre[6:0] acquisition aadacq[6:0] pre-charge aadpre[6:0] acquisition aadacq[6:0] aadres1l/h first result written to aadres0l/h anx digital ?1? out go/done 1-127 t inst 1-127 t inst 1-127 t inst t pre t acq t conv (1) (1) (1) (1) 2 inst t pre t acq t conv adstat[2:0] 3?b001 3?b010 3?b011 3?b101 3?b110 3?b111 3?b000 analog input trisx control analog input trisx control digital ?1? out adgrda guard a initialized adgrdb guard b initialized guard a initialized guard b initialized (adeppol = 1 ) chold (adippol = 0 ) shorted to v refl hold during conversion shorted to v refl hold during conversion charge sharing charge sharing
pic16(l)f1512/3 ds41624b-page 150 preliminary ? 2012 microchip technology inc. 16.6.8 guard ring outputs guard ring drive is a pair of digital outputs from the adc module. this function is enabled by the grdaoe and grdboe bits of the aadgrd register. polarity of the output is controlled by the grdpol bit. the guard ring outputs of the adc are active at all times. the outputs are initialized at the start of the pre- charge stage to match the polarity of the grdpol bit. the guard output signal changes polarity at the start of the acquisition stage. the value stored by the grdpol bit does not change. when in double sampling mode, the guard ring output does not initialize on the second conversion. it toggles polarity at the start of the first acquisition stage and again for the second acquisition, back to the original state. for more information on the timing of the guard ring output refer to figure 16-8 and figure 16-10 . a typical guard ring circuit is displayed in figure 16-11 . c guard represents the capacitance of the guard ring trace placed on a pcb board. the user selects values for r a and r b that cause the voltage profile of c guard to match the selected channel during acquisition. figure 16-11: user guard ring circuit 16.6.9 additional sample and hold capacitor additional capacitance can be added in parallel with the sample and hold capacitor (c hold ) by setting the addcap<2:0> bits of aadcap register. this bit connects additional capacitance to the adc conversion bus, increasing the effective internal capacitance of the a/d module and analog bus. the additional capacitance does not affect analog performance of the adc because it is not connected during conversion. see figure 16-12 . c guard r a r b adgrda adgrdb
? 2012 microchip technology inc. preliminary ds41624b-page 151 pic16(l)f1512/3 figure 16-12: a/d connection block diagram additional sample and hold cap v dd adout adoen (1) adc conversion bus adout pad adippol = 1 adippol = 0 addcap<2:0> (uses adc mux) v gnd anx anx pads v gnd v gnd v gnd note 1: adoen or adolen for pic16(l)f1512/3 devices.
pic16(l)f1512/3 ds41624b-page 152 preliminary ? 2012 microchip technology inc. 16.6.10 analog bus visibility the adoen and adolen bits of the aadcon3 register can be used to connect the adc conversion bus to the adout pin. this connection can be used to monitor the state and behavior of the internal analog bus. the adoen bit provides the connection via a standard channel passgate. the adloen bit provides a lower impedance connection. both bits can be enabled to provide the lowest impedance connection between the internal adc analog bus and the adout pin. the adout pin connection can be overridden during the pre-charge stage of conversion. this function is controlled by the adooen bit, which corresponds to the override enable signal. the polarity of the override is set by the adippol bit. 16.6.11 a/d double conversion procedure this is an example procedure for using the adc to perform a double analog-to-digital conversion: 1. configure port: ? disable pin output driver (refer to the tris register) ? configure pin as analog (refer to the ansel register) 2. configure the adc module: ? select adc conversion clock ? configure voltage reference ? select adc input channel ? turn on adc module ? set addsen bit 3. configure adc interrupt (optional): ? clear adc interrupt flag ? enable adc interrupt ? enable peripheral interrupt ? enable global interrupt (1) 4. wait the required acquisition time (2) . 5. start conversion by setting the go/done bit. 6. wait for adc conversions to complete by one of the following: ? polling the go/done bit ? waiting for the adc interrupt (interrupts enabled) 7. read adc result. ? conversion 1 result in aadres0h and aadres0l ? conversion 2 result in aadres1h and aadres1l 8. clear the adc interrupt flag (required if interrupt is enabled). 9. configure port: (required if pin is needed as an output) ? enable pin output driver (refer to the tris register) ? unconfigure pin as analog (refer to the ansel register) example 16-2: a/d double conversion note 1: the global interrupt can be disabled if the user is attempting to wake-up from sleep and resume in-line code execution. 2: refer to section 16.4 ?a/d acquisition requirements? . ;this code block configures the adc ;for polling, vdd and vss references, frc ;clock and an0 input. ; ;conversion start & polling for completion ; are included. ; banksel aadcon1; movlw b?11110000? ;right justify, frc ;clock movwf aadcon1 ;vdd and vss vref banksel trisa ; bsf trisa,0 ;set ra0 to input banksel ansel ; bsf ansel,0 ;set ra0 to analog banksel aadcon0 ; movlw b?00000001? ;select channel an0 movwf aadcon0 ;turn adc on call sampletime ;acquisiton delay bsf aadcon0,go/done ;start conversion btfsc aadcon0,go/done ;is conversion ;done? ;results of converions 1. goto $-1 ;no, test again banksel aadres0h ; movf aadres0h,w ;read upper 2 bits movwf resulthi ;store in gpr space banksel aadres0l ; movf aadres0l,w ;read lower 8 bits movwf resultlo ;store in gpr space ;results of converions 2. goto $-1 ;no, test again banksel aadres1h ; movf aadres1h,w ;read upper 2 bits movwf resulthi ;store in gpr space banksel aadres1l ; movf aadres1l,w ;read lower 8 bits movwf resultlo ;store in gpr space
? 2012 microchip technology inc. preliminary ds41624b-page 153 pic16(l)f1512/3 16.7 register definitions: adc control register 16-7: aadcon0: a/ d control register 0 (1) u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? chs<4:0> go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-2 chs<4:0>: analog channel select bits 11111 = fvr (fixed voltage reference) buffer 1 output (2) 11110 = reserved. no channel connected. 11101 = temperature indicator (3) . 11100 = reserved. no channel connected. 11011 =v refl (adc negative reference) 11010 =v refh (adc positive reference) (4) 11001 = reserved. no channel connected. ? ? ? 10100 = reserved. no channel connected. 10011 =an19 10010 =an18 10001 =an17 10000 =an16 01111 =an15 01110 =an14 01101 =an13 01100 =an12 01011 =an11 01010 =an10 01001 =an9 01000 =an8 00111 = reserved. no channel connected. 00110 = reserved. no channel connected. 00101 = reserved. no channel connected. 00100 =an4 00011 =an3 00010 =an2 00001 =an1 00000 =an0 bit 1 go/done : a/d conversion status bit 1 = a/d conversion cycle in progress. setting this bit starts an a/d conversion cycle. this bit is automatically cleared by hardware when the a/d conversion has completed. 0 = a/d conversion completed/not in progress bit 0 adon: adc enable bit 1 = adc is enabled 0 = adc is disabled and consumes no operating current note 1: see section 16.5.1 ?adc register mapping? for more information. 2: see section 14.0 ?fixed voltage reference (fvr)? for more information. 3: see section 15.0 ?temperature indicator module? for more information. 4: conversion results for the v refh node may contain errors due to noise.
pic16(l)f1512/3 ds41624b-page 154 preliminary ? 2012 microchip technology inc. register 16-8: aadcon1: a/ d control register 1 (1) r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 adfm adcs<2:0> ? ? adpref<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 adfm: a/d result format select bit 1 = right justified. six most significant bits of aadresxh are set to ? 0 ? when the conversion result is loaded. 0 = left justified. six least significant bits of aadresxl are set to ? 0 ? when the conversion result is loaded. bit 6-4 adcs<2:0>: a/d conversion clock select bits 111 =f rc (clock supplied from a dedicated rc oscillator) 110 =f osc /64 101 =f osc /16 100 =f osc /4 011 =f rc (clock supplied from a dedicated rc oscillator) 010 =f osc /32 001 =f osc /8 000 =f osc /2 bit 3-2 unimplemented: read as ? 0 ? bit 1-0 adpref<1:0>: a/d positive voltage reference configuration bits 11 =v ref is connected to internal fixed voltage reference (fvr) module (2) 10 =v ref is connected to external v ref + pin 01 = reserved 00 =v ref is connected to v dd note 1: see section 16.5.1 ?adc register mapping? for more information. 2: when selecting the fvr or the v ref + pin as the source of the positive reference, be aware that a minimum voltage specification exists. see section 25.0 ?electrical specifications? for details.
? 2012 microchip technology inc. preliminary ds41624b-page 155 pic16(l)f1512/3 register 16-9: aadcon2: a/ d control register 2 u-0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 u-0 ? trigsel<2:0> ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-4 trigsel<2:0>: adc special event trigger source selection bits 111 = reserved. auto-conversion trigger disabled. 110 = reserved. auto-conversion trigger disabled. 101 = tmr2 match to pr2 100 = tmr1 overflow 011 = tmr0 overflow 010 = ccp2 001 = ccp1 000 = no auto conversion trigger selection bits (1,2) bit 3-0 unimplemented: read as ? 0 ? note 1: this is a rising edge sensitive input for all sources. 2: signal used to set the corresponding interrupt flag.
pic16(l)f1512/3 ds41624b-page 156 preliminary ? 2012 microchip technology inc. register 16-10: aadcon3: a/ d control register 3 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 adeppol adippol adolen adoen adooen ? adipen addsen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 adeppol: external pre-charge polarity bit (1) 1 = selected channel is shorted to v ddio during pre-charge time 0 = selected channel is shorted to v ss during pre-charge time bit 6 adippol: internal pre-charge polarity bit (1) 1 =c hold is shorted to v refh during pre-charge time 0 =c hold is shorted to v refl during pre-charge time bit 5 adolen: adout low-impedance output enable bit 1 = adout pin low-impedance connection to adc bus 0 = no external connection to adc bus bit 4 adoen: adout output enable bit 1 = adout pin is connected to adc bus (normal passgate) 0 = no external connection to adc bus bit 3 adooen: adout override enable bit 1 = adout pin is overridden during pre-charge with internal polarity value 0 = adout pin is not overridden bit 2 unimplemented: read as ? 0 ? bit 1 adipen: a/d invert polarity enable bit if addsen = 1 : 1 = the output value of the adeppo l, adippol, and grdpol bits used by the a/d are inverted for the second conversion 0 = the second a/d conversion proceeds like the first if addsen = 0 : this bit has no effect. bit 0 addsen: a/d double sample enable bit 1 = the a/d immediately starts a new conversion after completing a conversion. go/done bit is not automatically clear at end of conversion 0 = a/d operates in the traditional, single conversion mode note 1: when the addsen = 1 and adipen = 1 ; the polarity of this output is inverted for the second conversion time. the stored bit value does not change.
? 2012 microchip technology inc. preliminary ds41624b-page 157 pic16(l)f1512/3 register 16-11: aadstat: a/d status register register 16-12: aadpre: a/d pre-charge cont rol register u-0 u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? ? ? ?adconv adstg<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-3 unimplemented: read as ? 0 ? bit 2 adconv: a/d conversion status bit 1 = indicates a/d in conversion sequence for aadres1h:aadres1l 0 = indicates a/d in conversion sequence for aadres0h:aadres0l (also reads ? 0 ? when go/done = 0 ) bit 1-0 adstg<1:0>: a/d stage status bits 11 = a/d module is in conversion stage 10 = a/d module is in acquisition stage 01 = a/d module is in pre-charge stage 00 = a/d module is not converting (same as go/done = 0 ) u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? adpre<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-0 adpre<6:0>: pre-charge time select bits (1) 111 1111 = pre-charge for 127 instruction cycles 111 1110 = pre-charge for 126 instruction cycles ? ? ? 000 0001 = pre-charge for 1 instruction cycle (fosc/4) 000 0000 = adc pre-charge time is disabled note 1: when the frc clock is selected as the conversion clock source, it is also the clock used for the pre-charge and acquisition times.
pic16(l)f1512/3 ds41624b-page 158 preliminary ? 2012 microchip technology inc. register 16-13: aadacq: a/d acquisi tion time control register register 16-14: aadgrd: a/d guard ring control register u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? adacq<6:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-0 adacq<6:0>: acquisition/charge share time select bits (1) 111 1111 = acquisition/charge share for 127 instruction cycles 111 1110 = acquisition/charge share for 126 instruction cycles ? ? ? 000 0001 = acquisition/charge share for one instruction cycle (fosc/4) 000 0000 = adc acquisition/charge share time is disabled note 1: when the frc clock is selected as the conversion clock source, it is also the clock used for the pre- charge and acquisition times. r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 u-0 u-0 grdboe (2) grdaoe (2) grdpol (1,2) ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 grdboe: guard ring b output enable bit (2) 1 = adc guard ring output is enabled to adgrdb pin. its corresponding trisx bit must be clear. 0 = no adc guard ring function to this pin is enabled bit 6 grdaoe: guard ring a output enable bit (2) 1 = adc guard ring output is enabled to adgrda pin. its corresponding trisx, x bit must be clear. 0 = no adc guard ring function is enabled bit 5 grdpol: guard ring polarity selection bit (1,2) 1 = adc guard ring outputs start as digital high during pre-charge stage 0 = adc guard ring outputs start as digital low during pre-charge stage bit 4-0 unimplemented: read as ? 0 ? note 1: when the addsen = 1 and adipen = 1 ; the polarity of this output is inverted for the second conversion time. the stored bit value does not change. 2: guard ring outputs are maintained while adon = 1 . the adgrda output switches polarity at the start of the acquisition time.
? 2012 microchip technology inc. preliminary ds41624b-page 159 pic16(l)f1512/3 register 16-15: aadcap: a/d additional sa mple capacitor selection register u-0 u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 ? addcap<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-3 unimplemented: read as ? 0 ? bit 2-0 addcap: adc additional sample capacitor selection bits 111 = nominal additional sample capacitor of 28 pf 110 = nominal additional sample capacitor of 24 pf 101 = nominal additional sample capacitor of 20 pf 100 = nominal additional sample capacitor of 16 pf 011 = nominal additional sample capacitor of 12 pf 010 = nominal additional sample capacitor of 8 pf 001 = nominal additional sample capacitor of 4 pf 000 = additional sample capacitor is disabled
pic16(l)f1512/3 ds41624b-page 160 preliminary ? 2012 microchip technology inc. register 16-16: aadresxh: adc result register msb adfm = 0 (1) r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adresx<9:2> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 ad<9:2> : most significant a/d results note 1: see section 16.5.1 ?adc register mapping? for more information. register 16-17: aadresxl: adc result register lsb adfm = 0 (1) r/w-x/u r/w-x/u u-0 u-0 u-0 u-0 u-0 u-0 adresx<1:0> ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 ad<1:0> : adc result register bits lower two bits of 10-bit conversion result bit 5-0 reserved : do not use. note 1: see section 16.5.1 ?adc register mapping? for more information.
? 2012 microchip technology inc. preliminary ds41624b-page 161 pic16(l)f1512/3 register 16-18: aadresxh: adc result register msb adfm = 1 (1) u-0 u-0 u-0 u-0 u-0 u-0 r/w-x/u r/w-x/u ? ? ? ? ? ? adresx<9:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-2 reserved : do not use. bit 1-0 ad<9:8> : most significant a/d results note 1: see section 16.5.1 ?adc register mapping? for more information. register 16-19: aadresxl: adc result register lsb adfm = 1 (1) r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adresx<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 ad<7:0> : adc result register bits lower two bits of 10-bit conversion result note 1: see section 16.5.1 ?adc register mapping? for more information.
pic16(l)f1512/3 ds41624b-page 162 preliminary ? 2012 microchip technology inc. table 16-6: summary of registers associated with adc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page aadcap ? ? ? ? ? addcap<2:0> 159 aadcon0 ?chs<4:0> go/done adon 153 aadcon1 adfm adcs<2:0> ? ? adpref<1:0> 154 aadcon2 ?trigsel<2:0> ? ? ? ? 155 aadcon3 adeppol adippol adolen adoen adooen ? adipen addsen 156 aadgrd grdboe grdaoe grdpol ? ? ? ? ? 158 aadpre ? adpre<6:0> 157 aadres0h a/d result 0 register high 160 aadres0l a/d result 0 register low 160 aadres1h a/d result 1 register high 160 aadres1l a/d result 1 register low 160 aadstat ? ? ? ? ? adconv adstg<1:0> 157 aadacq ? adacq<6:0> 158 ansela ? ?ansa5 ? ansa3 ansa2 ansa1 ansa0 109 anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 113 anselc ansc7 ansc6 ansc5 ansc4 ansc3 ansc2 ? ? 116 ccp1con ? ? dc1b<1:0> ccp1m<3:0> 246 ccp2con ? ? dc2b<1:0> ccp2m<3:0> 246 fvrcon fvren fvrrdy tsen tsrng ? ?adfvr<1:0> 126 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 108 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 112 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 115 legend: ? = unimplemented read as ? 0 ?. shaded cells are not used for adc module.
? 2012 microchip technology inc. preliminary ds41624b-page 163 pic16(l)f1512/3 17.0 timer0 module the timer0 module is an 8-bit timer/counter with the following features: ? 8-bit timer/counter register (tmr0) ? 8-bit prescaler (independent of watchdog timer) ? programmable internal or external clock source ? programmable external clock edge selection ? interrupt on overflow ? tmr0 can be used to gate timer1 figure 17-1 is a block diagram of the timer0 module. 17.1 timer0 operation the timer0 module can be used as either an 8-bit timer or an 8-bit counter. 17.1.1 8-bit timer mode the timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit timer mode is selected by clearing the tmr0cs bit of the option_reg register. when tmr0 is written, the increment is inhibited for two instruction cycles immediately following the write. 17.1.2 8-bit counter mode in 8-bit counter mode, the timer0 module will increment on every rising or falling edge of the t0cki pin. 8-bit counter mode using the t0cki pin is selected by setting the tmr0cs bit in the option_reg register to ? 1 ?. the rising or falling transition of the incrementing edge for either input source is determined by the tmr0se bit in the option_reg register. figure 17-1: block diagra m of the timer0 note: the value written to the tmr0 register can be adjusted, in order to account for the two instruction cycle delay when tmr0 is written. t0cki tmr0se tmr0 ps<2:0> data bus set flag bit tmr0if on overflow tmr0cs 0 1 0 1 8 8 8-bit prescaler f osc /4 psa sync 2 t cy overflow to timer1
pic16(l)f1512/3 ds41624b-page 164 preliminary ? 2012 microchip technology inc. 17.1.3 software programmable prescaler a software programmable prescaler is available for exclusive use with timer0. the prescaler is enabled by clearing the psa bit of the option_reg register. there are 8 prescaler options for the timer0 module ranging from 1:2 to 1:256. the prescale values are selectable via the ps<2:0> bits of the option_reg register. in order to have a 1:1 prescaler value for the timer0 module, the prescaler must be disabled by setting the psa bit of the option_reg register. the prescaler is not readable or writable. all instructions writing to the tmr0 register will clear the prescaler. 17.1.4 timer0 interrupt timer0 will generate an interrupt when the tmr0 register overflows from ffh to 00h. the tmr0if interrupt flag bit of the intcon register is set every time the tmr0 register overflows, regardless of whether or not the timer0 interrupt is enabled. the tmr0if bit can only be cleared in software. the timer0 interrupt enable is the tmr0ie bit of the intcon register. 17.1.5 8-bit counter mode synchronization when in 8-bit counter mode, the incrementing edge on the t0cki pin must be synchronized to the instruction clock. synchronization can be accomplished by sampling the prescaler output on the q2 and q4 cycles of the instruction clock. the high and low periods of the external clocking source must meet the timing requirements as shown in section 25.0 ?electrical specifications? . 17.1.6 operation during sleep timer0 cannot operate while the processor is in sleep mode. the contents of the tmr0 register will remain unchanged while the processor is in sleep mode. note: the watchdog timer (wdt) uses its own independent prescaler. note: the timer0 interrupt cannot wake the processor from sleep since the timer is frozen during sleep.
? 2012 microchip technology inc. preliminary ds41624b-page 165 pic16(l)f1512/3 17.2 option and timer0 control register table 17-1: summary of registers associated with timer0 register 17-1: option_reg: option register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 wpuen intedg tmr0cs tmr0se psa ps<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 wpuen : weak pull-up enable bit 1 = all weak pull-ups are disabled (except mclr , if it is enabled) 0 = weak pull-ups are enabled by individual wpux latch values bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of int pin 0 = interrupt on falling edge of int pin bit 5 tmr0cs: timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (f osc /4) bit 4 tmr0se: timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is not assigned to the timer0 module 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 165 tmr0 timer0 module register 163 * trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 108 legend: ? = unimplemented locations, read as ? 0 ?. shaded cells are not used by the timer0 module. * page provides register information. 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 bit value timer0 rate
pic16(l)f1512/3 ds41624b-page 166 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds41624b-page 167 pic16(l)f1512/3 18.0 timer1 module with gate control the timer1 module is a 16-bit timer/counter with the following features: ? 16-bit timer/counter register pair (tmr1h:tmr1l) ? programmable internal or external clock source ? 2-bit prescaler ? 32 khz secondary oscillator circuit ? optionally synchronized comparator out ? multiple timer1 gate (count enable) sources ? interrupt on overflow ? wake-up on overflow (external clock, asynchronous mode only) ? time base for the capture/compare function ? special event trigger (with ccp) ? selectable gate source polarity ? gate toggle mode ? gate single-pulse mode ? gate value status ? gate event interrupt figure 18-1 is a block diagram of the timer1 module. figure 18-1: timer1 block diagram tmr1h tmr1l t1sync t1ckps<1:0> prescaler 1, 2, 4, 8 0 1 synchronized clock input 2 set flag bit tmr1if on overflow tmr1 (2) tmr1on note 1: st buffer is high speed type when using t1cki. 2: timer1 register increments on rising edge. 3: synchronize does not operate while in sleep. t1g secondary f osc /4 internal clock sosco/t1cki sosci t1oscen 1 0 tmr1cs<1:0> (1) synchronize (3) det sleep input tmr1ge 0 1 00 01 10 t1gpol d q ck q 0 1 t1gval t1gtm single pulse acq. control t1gspm t1ggo/done t1gss<1:0> en out 10 11 00 01 f osc internal clock r d en q q1 rd t1gcon data bus det interrupt tmr1gif set t1clk f osc /2 internal clock d en q t1g_in tmr1on lfintosc from timer0 overflow from timer2 to clock switching modules 11 match pr2 reserved oscillator
pic16(l)f1512/3 ds41624b-page 168 preliminary ? 2012 microchip technology inc. 18.1 timer1 operation the timer1 module is a 16-bit incrementing counter which is accessed through the tmr1h:tmr1l register pair. writes to tmr1h or tmr1l directly update the counter. when used with an internal clock source, the module is a timer and increments on every instruction cycle. when used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. timer1 is enabled by configuring the tmr1on and tmr1ge bits in the t1con and t1gcon registers, respectively. table 18-1 displays the timer1 enable selections. 18.2 clock source selection the tmr1cs<1:0> and t1oscen bits of the t1con register are used to select the clock source for timer1. table 18-2 displays the clock source selections. 18.2.1 internal clock source when the internal clock source is selected the tmr1h:tmr1l register pair will increment on multiples of f osc as determined by the timer1 prescaler. when the f osc internal clock source is selected, the timer1 register value will in crement by four counts every instruction clock cycle. due to this condition, a 2 lsb error in resolution will occur when reading the timer1 value. to utilize the full resolution of timer1, an asynchronous input signal must be used to gate the timer1 clock input. the following asynchronous source may be used: ? asynchronous event on the t1g pin to timer1 gate 18.2.2 external clock source when the external clock source is selected, the timer1 module may work as a timer or a counter. when enabled to count, timer1 is incremented on the rising edge of the external clock input t1cki. this external clock source can be synchronized to the microcontroller system clock and run asynchronously. when used as a timer with a clock oscillator, an external 32.768 khz crystal can be used in conjunction with the secondary oscillator circuit. table 18-1: timer1 enable selections tmr1on tmr1ge timer1 operation 00 off 01 off 10 always on 11 count enabled note: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: ? timer1 enabled after por ? write to tmr1h or tmr1l ? timer1 is disabled ? timer1 is disabled (tmr1on = 0 ) when t1cki is high then timer1 is enabled (tmr1on= 1 ) when t1cki is low. table 18-2: clock source selections tmr1cs1 tmr1cs0 t1oscen clock source 11x lfintosc 101 secondary oscillator circuit on sosci/sosco pins 100 external clocking on t1cki pin 01x system clock (f osc ) 00x instruction clock (f osc /4)
? 2012 microchip technology inc. preliminary ds41624b-page 169 pic16(l)f1512/3 18.3 timer1 prescaler timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. the t1ckps bits of the t1con register control the prescale counter. the prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to tmr1h or tmr1l. 18.4 secondary oscillator timer1 uses the low-power secondary oscillator circuit on pins sosci and sosco. the secondary oscillator is designed to use an external 32.768 khz crystal. the secondary oscillator circuit is enabled by setting the t1oscen bit of the t1con register. the oscillator will continue to run during sleep. 18.5 timer1 operation in asynchronous counter mode if control bit t1sync of the t1con register is set, the external clock input is not synchronized. the timer increments asynchronously to the internal phase clocks. if the external clock source is selected then the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake-up the processor. however, special precautions in software are needed to read/write the timer (see section 18.5.1 ?reading and writing timer1 in asynchronous counter mode? ). 18.5.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write contention may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the tmr1h:tmr1l register pair. 18.6 timer1 gate timer1 can be configured to count freely or the count can be enabled and disabled using timer1 gate circuitry. this is also referred to as timer1 gate enable. timer1 gate can also be driven by multiple selectable sources. 18.6.1 timer1 gate enable the timer1 gate enable mode is enabled by setting the tmr1ge bit of the t1gcon register. the polarity of the timer1 gate enable mode is configured using the t1gpol bit of the t1gcon register. when timer1 gate enable mode is enabled, timer1 will increment on the rising edge of the timer1 clock source. when timer1 gate enable mode is disabled, no incrementing will occur and timer1 will hold the current count. see figure 18-3 for timing details. 18.6.2 timer1 gate source selection the timer1 gate source can be selected from one of four different sources. source selection is controlled by the t1gss bits of the t1gcon register. the polarity for each available source is also selectable. polarity selection is controlled by the t1gpol bit of the t1gcon register. table 18-4: timer1 gate sources note: the oscillator requires a start-up and stabilization time before use. thus, t1oscen should be set and a suitable delay observed prior to using timer1. a suitable delay similar to the ost delay can be implemented in software by clearing the tmr1if bit then presetting the tmr1h:tmr1l register pair to fc00h. the tmr1if flag will be set when 1024 clock cycles have elapsed, thereby indicating that the oscillator is running and reasonably stable. note: when switching from synchronous to asynchronous operation, it is possible to skip an increment. when switching from asynchronous to synchronous operation, it is possible to produce an additional increment. table 18-3: timer1 gate enable selections t1clk t1gpol t1g timer1 operation ? 00 counts ? 01 holds count ? 10 holds count ? 11 counts t1gss timer1 gate source 00 timer1 gate pin 01 overflow of timer0 (tmr0 increments from ffh to 00h) 10 timer2 match pr2 11 reserved
pic16(l)f1512/3 ds41624b-page 170 preliminary ? 2012 microchip technology inc. 18.6.2.1 t1g pin gate operation the t1g pin is one source for timer1 gate control. it can be used to supply an external source to the timer1 gate circuitry. 18.6.2.2 timer0 overflow gate operation when timer0 increments from ffh to 00h, a low-to-high pulse will automatically be generated and internally supplied to the timer1 gate circuitry. 18.6.2.3 timer2 match pr2 operation when timer2 increments and matches pr2, a low-to-high pulse will automatically be generated and internally supplied to the timer1 gate circuitry. 18.6.3 timer1 gate toggle mode when timer1 gate toggle mode is enabled, it is possible to measure the full-cycle length of a timer1 gate signal, as opposed to the duration of a single level pulse. the timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. see figure 18-4 for timing details. timer1 gate toggle mode is enabled by setting the t1gtm bit of the t1gcon register. when the t1gtm bit is cleared, the flip-flop is cleared and held clear. this is necessary in order to control which edge is measured. 18.6.4 timer1 gate single-pulse mode when timer1 gate single-pulse mode is enabled, it is possible to capture a single-pulse gate event. timer1 gate single-pulse mode is first enabled by setting the t1gspm bit in the t1gcon register. next, the t1ggo/done bit in the t1gcon register must be set. the timer1 will be fully enabled on the next incrementing edge. on the next trailing edge of the pulse, the t1ggo/done bit will automatically be cleared. no other gate events will be allowed to increment timer1 until the t1ggo/done bit is once again set in software. see figure 18-5 for timing details. if the single-pulse gate mode is disabled by clearing the t1gspm bit in the t1gcon register, the t1ggo/done bit should also be cleared. enabling the toggle mode and the single-pulse mode simultaneously will permit both sections to work together. this allows the cycle times on the timer1 gate source to be measured. see figure 18-6 for timing details. 18.6.5 timer1 gate value status when timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. the value is stored in the t1gval bit in the t1gcon register. the t1gval bit is valid even when the timer1 gate is not enabled (tmr1ge bit is cleared). 18.6.6 timer1 gate event interrupt when timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. when the falling edge of t1gval occurs, the tmr1gif flag bit in the pir1 register will be set. if the tmr1gie bit in the pie1 register is set, then an interrupt will be recognized. the tmr1gif flag bit operates even when the timer1 gate is not enabled (tmr1ge bit is cleared). note: enabling toggle mode at the same time as changing the gate polarity may result in indeterminate operation.
? 2012 microchip technology inc. preliminary ds41624b-page 171 pic16(l)f1512/3 18.7 timer1 interrupt the timer1 register pair (tmr1h:tmr1l) increments to ffffh and rolls over to 0000h. when timer1 rolls over, the timer1 interrupt flag bit of the pir1 register is set. to enable the interrupt on rollover, you must set these bits: ? tmr1on bit of the t1con register ? tmr1ie bit of the pie1 register ? peie bit of the intcon register ? gie bit of the intcon register the interrupt is cleared by clearing the tmr1if bit in the interrupt service routine. 18.8 timer1 operation during sleep timer1 can only operate during sleep when setup in asynchronous counter mode. in this mode, an external crystal or clock source can be used to increment the counter. to set up the timer to wake the device: ? tmr1on bit of the t1con register must be set ? tmr1ie bit of the pie1 register must be set ? peie bit of the intcon register must be set ? t1sync bit of the t1con register must be set ? tmr1cs bits of the t1con register must be configured ? t1oscen bit of the t1con register must be configured the device will wake-up on an overflow and execute the next instructions. if the gie bit of the intcon register is set, the device will call the interrupt service routine. timer1 secondary oscillator will continue to operate in sleep regardless of the t1sync bit setting. 18.9 ccp capture/compare time base the ccp modules use the tmr1h:tmr1l register pair as the time base when operating in capture or compare mode. in capture mode, the value in the tmr1h:tmr1l register pair is copied into the ccpr1h:ccpr1l register pair on a configured event. in compare mode, an event is triggered when the value ccpr1h:ccpr1l register pair matches the value in the tmr1h:tmr1l register pair. this event can be a special event trigger. for more information, see section 21.0 ?capture/compare/pwm modules? . 18.10 ccp special event trigger when the ccp is configured to trigger a special event, the trigger will clear the tmr1h:tmr1l register pair. this special event does not cause a timer1 interrupt. the ccp module may still be configured to generate a ccp interrupt. in this mode of operation, the ccpr1h:ccpr1l register pair becomes the period register for timer1. timer1 should be synchronized and f osc /4 should be selected as the clock source in order to utilize the special event trigger. asynchronous operation of timer1 can cause a special event trigger to be missed. in the event that a write to tmr1h or tmr1l coincides with a special event trigger from the ccp, the write will take precedence. for more information, see section 16.2.5 ?special event trigger? . figure 18-2: timer1 incrementing edge note: the tmr1h:tmr1l register pair and the tmr1if bit should be cleared before enabling interrupts. t1cki = 1 when tmr1 enabled t1cki = 0 when tmr1 enabled note 1: arrows indicate counter increments. 2: in counter mode, a falling edge must be registered by the count er prior to the first incrementing rising edge of the clock.
pic16(l)f1512/3 ds41624b-page 172 preliminary ? 2012 microchip technology inc. figure 18-3: timer1 gate enable mode figure 18-4: timer1 gate toggle mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 n n + 1 n + 2 n + 3 n + 4 tmr1ge t1gpol t1gtm t1g_in t1cki t1gval timer1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8
? 2012 microchip technology inc. preliminary ds41624b-page 173 pic16(l)f1512/3 figure 18-5: timer1 gate single-pulse mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 n n + 1 n + 2 t1gspm t1ggo/ done set by software cleared by hardware on falling edge of t1gval set by hardware on falling edge of t1gval cleared by software cleared by software tmr1gif counting enabled on rising edge of t1g
pic16(l)f1512/3 ds41624b-page 174 preliminary ? 2012 microchip technology inc. figure 18-6: timer1 gate single-pulse and toggle combined mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 nn + 1 n + 2 t1gspm t1ggo/ done set by software cleared by hardware on falling edge of t1gval set by hardware on falling edge of t1gval cleared by software cleared by software tmr1gif t1gtm counting enabled on rising edge of t1g n + 4 n + 3
? 2012 microchip technology inc. preliminary ds41624b-page 175 pic16(l)f1512/3 18.11 timer1 control register the timer1 control register (t1con), shown in register 18-1 , is used to control timer1 and select the various features of the timer1 module. register 18-1: t1con: ti mer1 control register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u u-0 r/w-0/u tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ?tmr1on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 tmr1cs<1:0>: timer1 clock source select bits 11 = timer1 clock source is lfintosc 10 = timer1 clock source is pin or oscillator: if t1oscen = 0 : external clock from t1cki pin (on the rising edge) if t1oscen = 1 : crystal oscillator on sosci/sosco pins 01 = timer1 clock source is system clock (f osc ) 00 = timer1 clock source is instruction clock (f osc /4) bit 5-4 t1ckps<1:0>: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: lp oscillator enable control bit 1 = secondary oscillator circuit enabled for timer1 0 = secondary oscillator circuit disabled for timer1 bit 2 t 1sync : timer1 external clock input synchronization control bit tmr1cs<1:0> = 1x 1 = do not synchronize external clock input 0 = synchronize external clock input with system clock (f osc ) tmr1cs<1:0> = 0x this bit is ignored. timer1 uses the internal clock when tmr1cs<1:0> = 1x . bit 1 unimplemented: read as ? 0 ? bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 clears timer1 gate flip-flop
pic16(l)f1512/3 ds41624b-page 176 preliminary ? 2012 microchip technology inc. 18.12 timer1 gate control register the timer1 gate control register (t1gcon), shown in register 18-2 , is used to control timer1 gate. register 18-2: t1gcon: timer1 gate control register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w/hc-0/u r-x/x r/w-0/u r/w-0/u tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hc = bit is cleared by hardware bit 7 tmr1ge: timer1 gate enable bit if tmr1on = 0 : this bit is ignored if tmr1on = 1 : 1 = timer1 counting is controlled by the timer1 gate function 0 = timer1 counts regardless of timer1 gate function bit 6 t1gpol: timer1 gate polarity bit 1 = timer1 gate is active-high (timer1 counts when gate is high) 0 = timer1 gate is active-low (timer1 counts when gate is low) bit 5 t1gtm: timer1 gate toggle mode bit 1 = timer1 gate toggle mode is enabled 0 = timer1 gate toggle mode is disabled and toggle flip-flop is cleared timer1 gate flip-flop toggles on every rising edge. bit 4 t1gspm: timer1 gate single-pulse mode bit 1 = timer1 gate single-pulse mode is enabled and is controlling timer1 gate 0 = timer1 gate single-pulse mode is disabled bit 3 t1ggo/done : timer1 gate single-pulse acquisition status bit 1 = timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = timer1 gate single-pulse acquisition has completed or has not been started bit 2 t1gval: timer1 gate current state bit indicates the current state of the timer1 gate that could be provided to tmr1h:tmr1l. unaffected by timer1 gate enable (tmr1ge). bit 1-0 t1gss<1:0>: timer1 gate source select bits 00 = timer1 gate pin 01 = timer0 overflow output 10 = timer2 match pr2 11 = reserved
? 2012 microchip technology inc. preliminary ds41624b-page 177 pic16(l)f1512/3 table 18-5: summary of registers associated with timer1 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselb ? ? ansb5 ansb4 ansb3 ansb2 ansb1 ansb0 113 ccp1con ? ? dc1b<1:0> ccp1m<3:0> 246 ccp2con ? ? dc2b<1:0> ccp2m<3:0> 246 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 tmr1h holding register for the most significant byte of the 16-bit tmr1 count 171 * tmr1l holding register for the least significant byte of the 16-bit tmr1 count 171 * trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 113 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 116 t1con tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ?tmr1on 175 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss<1:0> 176 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used by the timer1 module. * page provides register information.
pic16(l)f1512/3 ds41624b-page 178 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds41624b-page 179 pic16(l)f1512/3 19.0 timer2 module the timer2 module incorporates the following features: ? 8-bit timer and period registers (tmr2 and pr2, respectively) ? readable and writable (both registers) ? software programmable prescaler (1:1, 1:4, 1:16, and 1:64) ? software programmable postscaler (1:1 to 1:16) ? interrupt on tmr2 match with pr2, respectively ? optional use as the shift clock for the mssp modules see figure 19-1 for a block diagram of timer2. figure 19-1: timer2 block diagram comparator tmr2 reset postscaler prescaler pr2 2 f osc /4 1:1 to 1:16 1:1, 1:4, 1:16, 1:64 eq 4 t2outps<3:0> t2ckps<1:0> tmr2 output sets flag bit tmr2if
pic16(l)f1512/3 ds41624b-page 180 preliminary ? 2012 microchip technology inc. 19.1 timer2 operation the clock input to the timer2 modules is the system instruction clock (f osc /4). tmr2 increments from 00h on each clock edge. a 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. these options are selected by the prescaler control bits, t2ckps<1:0> of the t2con register. the value of tmr2 is compared to that of the period register, pr2, on each clock cycle. when the two values match, the comparator generates a match signal as the timer output. this signal also resets the value of tmr2 to 00h on the next cycle and drives the output counter/postscaler (see section 19.2 ?timer2 interrupt? ). the tmr2 and pr2 registers are both directly readable and writable. the tmr2 register is cleared on any device reset, whereas the pr2 register initializes to ffh. both the prescaler and postscaler counters are cleared on the following events: ? a write to the tmr2 register ? a write to the t2con register ? power-on reset (por) ? brown-out reset (bor) ?mclr reset ? watchdog timer (wdt) reset ? stack overflow reset ? stack underflow reset ? reset instruction 19.2 timer2 interrupt timer2 can also generate an optional device interrupt. the timer2 output signal (tmr2-to-pr2 match) provides the input for the 4-bit counter/postscaler. this counter generates the tmr2 match interrupt flag which is latched in tmr2if of the pir1 register. the interrupt is enabled by setting the tmr2 match interrupt enable bit, tmr2ie of the pie1 register. a range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, t2outps<3:0>, of the t2con register. 19.3 timer2 output the unscaled output of tmr2 is available primarily to the ccp module, where it is used as a time base for operations in pwm mode. timer2 can be optionally used as the shift clock source for the mssp module operating in spi mode. additional information is provided in section 20.0 ?master synchronous serial port (mssp) module? 19.4 timer2 operation during sleep timer2 cannot be operated while the processor is in sleep mode. the contents of the tmr2 and pr2 registers will remain unchanged while the processor is in sleep mode. note: tmr2 is not cleared when t2con is written.
? 2012 microchip technology inc. preliminary ds41624b-page 181 pic16(l)f1512/3 19.5 timer2 control register register 19-1: t2con: ti mer2 control register u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? t2outps<3:0> tmr2on t2ckps<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-3 t2outps<3:0>: timer2 output postscaler select bits 1111 = 1:16 postscaler 1110 = 1:15 postscaler 1101 = 1:14 postscaler 1100 = 1:13 postscaler 1011 = 1:12 postscaler 1010 = 1:11 postscaler 1001 = 1:10 postscaler 1000 = 1:9 postscaler 0111 = 1:8 postscaler 0110 = 1:7 postscaler 0101 = 1:6 postscaler 0100 = 1:5 postscaler 0011 = 1:4 postscaler 0010 = 1:3 postscaler 0001 = 1:2 postscaler 0000 = 1:1 postscaler bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps<1:0>: timer2 clock prescale select bits 11 = prescaler is 64 10 = prescaler is 16 01 =prescaler is 4 00 = prescaler is 1
pic16(l)f1512/3 ds41624b-page 182 preliminary ? 2012 microchip technology inc. table 19-1: summary of registers associated with timer2 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ccp1con ? ? dc1b<1:0> ccp1m<3:0> 246 ccp2con ? ? dc2b<1:0> ccp2m<3:0> 246 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 pr2 timer2 module period register 179 * t2con ? t2outps<3:0> tmr2on t2ckps<1:0> 181 tmr2 holding register for the 8-bit tmr2 register 179 * legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for timer2 module. * page provides register information.
? 2012 microchip technology inc. preliminary ds41624b-page 183 pic16(l)f1512/3 20.0 master synchronous serial port (mssp) module 20.1 master ssp (mssp) module overview the master synchronous serial port (mssp) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, display drivers, a/d converters, etc. the mssp module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c?) the spi interface supports the following modes and features: ?master mode ? slave mode ? clock parity ? slave select synchronization (slave mode only) ? daisy-chain connection of slave devices figure 20-1 is a block diagram of the spi interface module. figure 20-1: mssp block diagram (spi mode) ( ) read write data bus sspsr reg sspm<3:0> bit 0 shift clock ss control enable edge select clock select tmr2 output 2 edge select 2 (ckp, cke) 4 tris bit sdo sspbuf reg sdi ss sck t osc prescaler 4, 16, 64 baud rate generator (sspadd)
pic16(l)f1512/3 ds41624b-page 184 preliminary ? 2012 microchip technology inc. the i 2 c interface supports the following modes and features: ?master mode ? slave mode ? byte nacking (slave mode) ? limited multi-master support ? 7-bit and 10-bit addressing ? start and stop interrupts ? interrupt masking ? clock stretching ? bus collision detection ? general call address matching ?address masking ? address hold and data hold modes ? selectable sda hold times figure 20-2 is a block diagram of the i 2 c interface module in master mode. figure 20-3 is a diagram of the i 2 c interface module in slave mode. figure 20-2: mssp block diagram (i 2 c? master mode) read write sspsr start bit, stop bit, start bit detect, sspbuf internal data bus set/reset: s, p, sspstat, wcol, sspov shift clock msb lsb sda acknowledge generate (sspcon2) stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv scl scl in bus collision sda in receive enable (rcen) clock cntl clock arbitrate/bcol detect (hold off clock source) [sspm 3:0] baud rate reset sen, pen (sspcon2) generator (sspadd) address match detect set sspif, bclif
? 2012 microchip technology inc. preliminary ds41624b-page 185 pic16(l)f1512/3 figure 20-3: mssp block diagram (i 2 c? slave mode) read write sspsr reg match detect sspadd reg start and stop bit detect sspbuf reg internal data bus addr match set, reset s, p bits (sspstat reg) scl sda shift clock msb lsb sspmsk reg
pic16(l)f1512/3 ds41624b-page 186 preliminary ? 2012 microchip technology inc. 20.2 spi mode overview the serial peripheral interface (spi) bus is a synchronous serial data communication bus that operates in full duplex mode. devices communicate in a master/slave environment where the master device initiates the communication. a slave device is controlled through a chip select known as slave select. the spi bus specifies four signal connections: ? serial clock (sck) ? serial data out (sdo) ? serial data in (sdi) ? slave select (ss ) figure 20-1 shows the block diagram of the mssp module when operating in spi mode. the spi bus operates with a single master device and one or more slave devices. when multiple slave devices are used, an independent slave select connection is required from the master device to each slave device. figure 20-4 shows a typical connection between a master device and multiple slave devices. the master selects only one slave at a time. most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. with either the master or the slave device, data is always shifted out one bit at a time, with the most significant bit (msb) shifted out first. at the same time, a new least significant bit (lsb) is shifted into the same register. figure 20-5 shows a typical connection between two processors configured as master and slave devices. data is shifted out of both shift registers on the programmed clock edge and latched on the opposite edge of the clock. the master device transmits information out on its sdo output pin which is connected to, and received by, the slave?s sdi input pin. the slave device transmits information out on its sdo output pin, which is connected to, and received by, the master?s sdi input pin. to begin communication, the master device first sends out the clock signal. both the master and the slave devices should be configured for the same clock polarity. the master device starts a transmission by sending out the msb from its shift register. the slave device reads this bit from that same line and saves it into the lsb position of its shift register. during each spi clock cycle, a full duplex data transmission occurs. this means that while the master device is sending out the msb from its shift register (on its sdo pin) and the slave device is reading this bit and saving it as the lsb of its shift register, that the slave device is also sending out the msb from its shift register (on its sdo pin) and the master device is reading this bit and saving it as the lsb of its shift register. after 8 bits have been shifted out, the master and slave have exchanged register values. if there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. whether the data is meaningful or not (dummy data), depends on the application software. this leads to three scenarios for data transmission: ? master sends useful data and slave sends dummy data. ? master sends useful data and slave sends useful data. ? master sends dummy data and slave sends useful data. transmissions may involve any number of clock cycles. when there is no more data to be transmitted, the master stops sending the clock signal and it deselects the slave. every slave device connected to the bus that has not been selected through its slave select line must disregard the clock and transmission signals and must not transmit out any data of its own.
? 2012 microchip technology inc. preliminary ds41624b-page 187 pic16(l)f1512/3 figure 20-4: spi master and multiple slave connection 20.2.1 spi mode registers the mssp module has five registers for spi mode operation. these are: ? mssp status register (sspstat) ? mssp control register 1 (sspcon1) ? mssp control register 3 (sspcon3) ? mssp data buffer register (sspbuf) ? mssp address register (sspadd) ? mssp shift register (sspsr) (not directly accessible) sspcon1 and sspstat are the control and status registers in spi mode operation. the sspcon1 register is readable and writable. the lower six bits of the sspstat are read-only. the upper two bits of the sspstat are read/write. in spi master mode, sspadd can be loaded with a value used in the baud rate generator. more information on the baud rate generator is available in section 20.7 ?baud rate generator? . sspsr is the shift register used for shifting data in and out. sspbuf provides indirect access to the sspsr register. sspbuf is the buffer register to which data bytes are written, and from which data bytes are read. in receive operations, sspsr and sspbuf together create a buffered receiver. when sspsr receives a complete byte, it is transferred to sspbuf and the sspif interrupt is set. during transmission, the sspbuf is not buffered. a write to sspbuf will write to both sspbuf and sspsr. 20.2.2 spi mode operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspcon1<5:0> and sspstat<7:6>). these control bits allow the following to be specified: ? master mode (sck is the clock output) ? slave mode (sck is the clock input) ? clock polarity (idle state of sck) ? data input sample phase (middle or end of data output time) ? clock edge (output data on rising/falling edge of sck) ? clock rate (master mode only) ? slave select mode (slave mode only) to enable the serial port, ssp enable bit, sspen of the sspcon1 register, must be set. to reset or reconfig- ure spi mode, clear the sspen bit, re-initialize the sspcon registers and then set the sspen bit. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the tris register) appropriately programmed as follows: ? sdi must have corresponding tris bit set ? sdo must have corresponding tris bit cleared ? sck (master mode) must have corresponding tris bit cleared ? sck (slave mode) must have corresponding tris bit set ?ss must have corresponding tris bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. spi master sck sdo sdi general i/o general i/o general i/o sck sdi sdo ss spi slave #1 sck sdi sdo ss spi slave #2 sck sdi sdo ss spi slave #3
pic16(l)f1512/3 ds41624b-page 188 preliminary ? 2012 microchip technology inc. the mssp consists of a transmit/receive shift register (sspsr) and a buffer register (sspbuf). the sspsr shifts the data in and out of the device, msb first. the sspbuf holds the data that was written to the sspsr until the received data is ready. once the eight bits of data have been received, that byte is moved to the sspbuf register. then, the buffer full detect bit, bf of the sspstat register, and the interrupt flag bit, sspif, are set. this double-buffering of the received data (sspbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspbuf register during transmission/reception of data will be ignored and the write collision detect bit wcol of the sspcon1 register, will be set. user software must clear the wcol bit to allow the following write(s) to the sspbuf register to complete successfully. when the application software is expecting to receive valid data, the sspbuf should be read before the next byte of data to transfer is written to the sspbuf. the buffer full bit, bf of the sspstat register, indicates when sspbuf has been loaded with the received data (transmission is complete). when the sspbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has completed. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. the sspsr is not directly readable or writable and can only be accessed by addressing the sspbuf register. additionally, the sspstat register indicates the various status conditions. figure 20-5: spi mast er/slave connection serial input buffer (buf) shift register (sspsr) msb lsb sdo sdi processor 1 sck spi master sspm<3:0> = 00xx serial input buffer (sspbuf) shift register (sspsr) lsb msb sdi sdo processor 2 sck spi slave sspm<3:0> = 010x serial clock ss slave select general i/o (optional) = 1010
? 2012 microchip technology inc. preliminary ds41624b-page 189 pic16(l)f1512/3 20.2.3 spi master mode the master can initiate the data transfer at any time because it controls the sck line. the master determines when the slave (processor 2, figure 20-5 ) is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspbuf register is written to. if the spi is only going to receive, the sdo output could be disabled (programmed as an input). the sspsr register will continue to shift in the signal present on the sdi pin at the programmed clock rate. as each byte is received, it will be loaded into the sspbuf register as if a normal received byte (interrupts and status bits appropriately set). the clock polarity is selected by appropriately programming the ckp bit of the sspcon1 register and the cke bit of the sspstat register. this then, would give waveforms for spi communication as shown in figure 20-6 , figure 20-9 and figure 20-10 , where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: ?f osc /4 (or t cy ) ?f osc /16 (or 4 * t cy ) ?f osc /64 (or 16 * t cy ) ? timer2 output/2 ? fosc/(4 * (sspadd + 1)) figure 20-6 shows the waveforms for master mode. when the cke bit is set, the sdo data is valid before there is a clock edge on sck. the change of the input sample is shown based on the state of the smp bit. the time when the sspbuf is loaded with the received data is shown. figure 20-6: spi mode waveform (master mode) sck (ckp = 0 sck (ckp = 1 sck (ckp = 0 sck (ckp = 1 4 clock modes input sample input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 sdi sspif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspbuf sspsr to sspbuf sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) bit 0
pic16(l)f1512/3 ds41624b-page 190 preliminary ? 2012 microchip technology inc. 20.2.4 spi slave mode in slave mode, the data is transmitted and received as external clock pulses appear on sck. when the last bit is latched, the sspif interrupt flag bit is set. before enabling the module in spi slave mode, the clock line must match the proper idle state. the clock line can be observed by reading the sck pin. the idle state is determined by the ckp bit of the sspcon1 register. while in slave mode, the external clock is supplied by the external clock source on the sck pin. this external clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. the shift register is clocked from the sck pin input and when a byte is received, the device will generate an interrupt. if enabled, the device will wake-up from sleep. 20.2.4.1 daisy-chain configuration the spi bus can sometimes be connected in a daisy-chain configuration. the first slave output is connected to the second slave input, the second slave output is connected to the third slave input, and so on. the final slave output is connected to the master input. each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. the whole chain acts as one large communication shift register. the daisy-chain feature only requires a single slave select line from the master device. figure 20-7 shows the block diagram of a typical daisy-chain connection when operating in spi mode. in a daisy-chain configuration, only the most recent byte on the bus is required by the slave. setting the boen bit of the sspcon3 register will enable writes to the sspbuf register, even if the previous byte has not been read. this allows the software to ignore data that may not apply to it. 20.2.5 slave select synchronization the slave select can also be used to synchronize communication. the slave select line is held high until the master device is ready to communicate. when the slave select line is pulled low, the slave knows that a new transmission is starting. if the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the slave select line returns to a high state. the slave is then ready to receive a new transmission when the slave select line is pulled low again. if the slave select line is not used, there is a risk that the slave will eventually become out of sync with the master. if the slave misses a bit, it will always be one bit off in future transmissions. use of the slave select line allows the slave and master to align themselves at the beginning of each transmission. the ss pin allows a synchronous slave mode. the spi must be in slave mode with ss pin control enabled (sspcon1<3:0> = 0100 ). when the ss pin is low, transmission and reception are enabled and the sdo pin is driven. when the ss pin goes high, the sdo pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. external pull-up/pull-down resistors may be desirable depending on the application. when the spi module resets, the bit counter is forced to ? 0 ?. this can be done by either forcing the ss pin to a high level or clearing the sspen bit. note 1: when the spi is in slave mode with ss pin control enabled (sspcon1<3:0> = 0100 ), the spi module will reset if the ss pin is set to v dd . 2: when the spi is used in slave mode with cke set; the user must enable ss pin control. 3: while operated in spi slave mode the smp bit of the sspstat register must remain clear.
? 2012 microchip technology inc. preliminary ds41624b-page 191 pic16(l)f1512/3 figure 20-7: spi daisy-chain connection figure 20-8: slave sele ct synchronous waveform spi master sck sdo sdi general i/o sck sdi sdo ss spi slave #1 sck sdi sdo ss spi slave #2 sck sdi sdo ss spi slave #3 sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 7 sspif interrupt cke = 0 ) cke = 0 ) write to sspbuf sspsr to sspbuf ss flag bit 0 bit 7 bit 0 bit 6 sspbuf to sspsr shift register sspsr and bit count are reset
pic16(l)f1512/3 ds41624b-page 192 preliminary ? 2012 microchip technology inc. figure 20-9: spi mode wavefo rm (slave mode with cke = 0 ) figure 20-10: spi mode wavefo rm (slave mode with cke = 1 ) sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt cke = 0 ) cke = 0 ) write to sspbuf sspsr to sspbuf ss flag optional bit 0 detection active write collision valid sck (ckp = 1 sck (ckp = 0 input sample sdi bit 7 bit 0 sdo bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspif interrupt cke = 1 ) cke = 1 ) write to sspbuf sspsr to sspbuf ss flag not optional write collision detection active valid
? 2012 microchip technology inc. preliminary ds41624b-page 193 pic16(l)f1512/3 20.2.6 spi operation in sleep mode in spi master mode, module clocks may be operating at a different speed than when in full-power mode; in the case of the sleep mode, all clocks are halted. special care must be taken by the user when the mssp clock is much faster than the system clock. in slave mode, when mssp interrupts are enabled, after the master completes sending data, an mssp interrupt will wake the controller from sleep. if an exit from sleep mode is not desired, mssp interrupts should be disabled. in spi master mode, when the sleep mode is selected, all module clocks are halted and the transmis- sion/reception will remain in that state until the device wakes. after the device returns to run mode, the module will resume transmitting and receiving data. in spi slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode and data to be shifted into the spi transmit/receive shift register. when all 8 bits have been received, the mssp interrupt flag bit will be set and if enabled, will wake the device. table 20-1: summary of registers as sociated with spi operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ansa5 ? ansa3 ansa2 ansa1 ansa0 109 anselc ansc7 ansc6 ansc5 ansc4 ansc3 ansc2 ? ? 116 apfcon ? ? ? ? ? ? sssel ccp2sel 106 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 sspbuf synchronous serial port receive buffer/transmit register 187 * sspcon1 wcol sspov sspen ckp sspm<3:0> 232 sspcon3 acktim pcie scie boen sdaht sbcde ahen dhen 234 sspstat smp cke d/a p s r/w ua bf 232 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 108 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 115 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the mssp in spi mode. * page provides register information.
pic16(l)f1512/3 ds41624b-page 194 preliminary ? 2012 microchip technology inc. 20.3 i 2 c mode overview the inter-integrated circuit bus (i 2 c) is a multi-master serial data communication bus. devices communicate in a master/slave environment where the master devices initiate the communication. a slave device is controlled through addressing. the i 2 c bus specifies two signal connections: ? serial clock (scl) ? serial data (sda) figure 20-2 and figure 20-3 show the block diagrams of the mssp module when operating in i 2 c mode. both the scl and sda connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. figure 20-11 shows a typical connection between two processors configured as master and slave devices. the i 2 c bus can operate with one or more master devices and one or more slave devices. there are four potential modes of operation for a given device: ? master transmit mode (master is transmitting data to a slave) ? master receive mode (master is receiving data from a slave) ?slave transmit mode (slave is transmitting data to a master) ? slave receive mode (slave is receiving data from the master) to begin communication, a master device starts out in master transmit mode. the master device sends out a start bit followed by the address byte of the slave it intends to communicate with. this is followed by a sin- gle read/write bit, which determines whether the mas- ter intends to transmit to or receive data from the slave device. if the requested slave exists on the bus, it will respond with an acknowledge bit, otherwise known as an ack . the master then continues in either transmit mode or receive mode and the slave continues in the complement, either in receive mode or transmit mode, respectively. a start bit is indicated by a high-to-low transition of the sda line while the scl line is held high. address and data bytes are sent out, most significant bit (msb) first. the read/write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. figure 20-11: i 2 c master/ slave connection the acknowledge bit (ack ) is an active-low signal, which holds the sda line low to indicate to the transmit- ter that the slave device has received the transmitted data and is ready to receive more. the transition of a data bit is always performed while the scl line is held low. transitions that occur while the scl line is held high are used to indicate start and stop bits. if the master intends to write to the slave, then it repeat- edly sends out a byte of data, with the slave responding after each byte with an ack bit. in this example, the master device is in master transmit mode and the slave is in slave receive mode. if the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ack bit. in this example, the master device is in master receive mode and the slave is slave transmit mode. on the last byte of data communicated, the master device may end the transmission by sending a stop bit. if the master device is in receive mode, it sends the stop bit in place of the last ack bit. a stop bit is indicated by a low-to-high transition of the sda line while the scl line is held high. in some cases, the master may want to maintain control of the bus and re-initiate another transmission. if so, the master device may send another start bit in place of the stop bit or last ack bit when it is in receive mode. the i 2 c bus specifies three message protocols; ? single message where a master writes data to a slave. ? single message where a master reads data from a slave. ? combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. master scl sda scl sda slave v dd v dd
? 2012 microchip technology inc. preliminary ds41624b-page 195 pic16(l)f1512/3 when one device is transmitting a logical one, or letting the line float, and a second device is transmitting a logical zero, or holding the line low, the first device can detect that the line is not a logical one. this detection, when used on the scl line, is called clock stretching. clock stretching gives slave devices a mechanism to control the flow of data. when this detection is used on the sda line, it is called arbitration. arbitration ensures that there is only one master device communicating at any single time. 20.3.1 clock stretching when a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. an addressed slave device may hold the scl clock line low after receiving or send- ing a bit, indicating that it is not yet ready to continue. the master that is communicating with the slave will attempt to raise the scl line in order to transfer the next bit, but will detect that the clock line has not yet been released. because the scl connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 20.3.2 arbitration each master device must monitor the bus for start and stop bits. if the device detects that the bus is busy, it cannot begin a new message until the bus returns to an idle state. however, two master devices may try to initiate a trans- mission on or about the same time. when this occurs, the process of arbitration begins. each transmitter checks the level of the sda data line and compares it to the level that it expects to find. the first transmitter to observe that the two levels do not match, loses arbitration, and must stop transmitting on the sda line. for example, if one transmitter holds the sda line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the sda line will be low. the first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. the first transmitter to notice this difference is the one that loses arbitration and must stop driving the sda line. if this transmitter is also a master device, it also must stop driving the scl line. it then can monitor the lines for a stop condition before trying to reissue its transmission. in the meantime, the other device that has not noticed any difference between the expected and actual levels on the sda line continues with its original transmission. it can do so without any complications, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. slave transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less common. if two master devices are sending a message to two different slave devices at the address stage, the master sending the lower slave address always wins arbitration. when two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration pro- cess must continue into the data stage. arbitration usually occurs very rarely, but it is a necessary process for proper multi-master support.
pic16(l)f1512/3 ds41624b-page 196 preliminary ? 2012 microchip technology inc. 20.4 i 2 c mode operation all mssp i 2 c communication is byte oriented and shifted out msb first. six sfr registers and 2 interrupt flags interface the module with the pic ? microcon- troller and user software. two pins, sda and scl, are exercised by the module to communicate with other external i 2 c devices. 20.4.1 byte format all communication in i 2 c is done in 9-bit segments. a byte is sent from a master to a slave or vice-versa, followed by an acknowledge bit sent back. after the 8th falling edge of the scl line, the device outputting data on the sda changes that pin to an input and reads in an acknowledge value on the next clock pulse. the clock signal, scl, is provided by the master. data is valid to change while the scl signal is low, and sampled on the rising edge of the clock. changes on the sda line while the scl line is high define special conditions on the bus, explained below. 20.4.2 definition of i 2 c terminology there is language and terminology in the description of i 2 c communication that have definitions specific to i 2 c. that word usage is defined below and may be used in the rest of this document without explanation. this table was adapted from the philips i 2 c specification. 20.4.3 sda and scl pins selection of any i 2 c mode with the sspen bit set, forces the scl and sda pins to be open-drain. these pins should be set by the user to inputs by setting the appropriate tris bits. 20.4.4 sda hold time the hold time of the sda pin is selected by the sdaht bit of the sspcon3 register. hold time is the time sda is held valid after the falling edge of scl. setting the sdaht bit selects a longer 300 ns minimum hold time and may help on buses with large capacitance. table 20-2: i 2 c bus terms note: data is tied to output zero when an i 2 c mode is enabled. term description transmitter the device which shifts data out onto the bus. receiver the device which shifts data in from the bus. master the device that initiates a transfer, generates clock signals and terminates a transfer. slave the device addressed by the master. multi-master a bus with more than one device that can initiate data transfers. arbitration procedure to ensure that only one master at a time controls the bus. winning arbitration ensures that the message is not corrupted. synchronization procedure to synchronize the clocks of two or more devices on the bus. idle no master is controlling the bus, and both sda and scl lines are high. active any time one or more master devices are controlling the bus. addressed slave slave device that has received a matching address and is actively being clocked by a master. matching address address byte that is clocked into a slave that matches the value stored in sspadd. write request slave receives a matching address with r/w bit clear, and is ready to clock in data. read request master sends an address byte with the r/w bit set, indicating that it wishes to clock data out of the slave. this data is the next and all following bytes until a restart or stop. clock stretching when a device on the bus hold scl low to stall communication. bus collision any time the sda line is sampled low by the module while it is outputting and expected high state.
? 2012 microchip technology inc. preliminary ds41624b-page 197 pic16(l)f1512/3 20.4.5 start condition the i 2 c specification defines a start condition as a transition of sda from a high to a low state while scl line is high. a start condition is always generated by the master and signifies the transition of the bus from an idle to an active state. figure 20-12 shows wave forms for start and stop conditions. a bus collision can occur on a start condition if the module samples the sda line low before asserting it low. this does not conform to the i 2 c specification that states no bus collision can occur on a start. 20.4.6 stop condition a stop condition is a transition of the sda line from low-to-high state while the scl line is high. 20.4.7 restart condition a restart is valid any time that a stop would be valid. a master can issue a restart if it wishes to hold the bus after terminating the current transfer. a restart has the same effect on the slave that a start would, resetting all slave logic and preparing it to clock in an address. the master may want to address the same or another slave. in 10-bit addressing slave mode a restart is required for the master to clock data out of the addressed slave. once a slave has been fully addressed, matching both high and low address bytes, the master can issue a restart and the high address byte with the r/w bit set. the slave logic will then hold the clock and prepare to clock out data. after a full match with r/w clear in 10-bit mode, a prior match flag is set and maintained. until a stop condition, a high address with r/w clear, or high address match fails. 20.4.8 start/stop condition interrupt masking the scie and pcie bits of the sspcon3 register can enable the generation of an interrupt in slave modes that do not typically support this function. slave modes where interrupt on start and stop detect are already enabled, these bits will have no effect. figure 20-12: i 2 c start and stop conditions figure 20-13: i 2 c restart condition note: at least one scl low time must appear before a stop is valid, therefore, if the sda line goes low then high again while the scl line stays high, only the start condition is detected. sda scl p stop condition s start condition change of data allowed change of data allowed restart condition sr change of data allowed change of data allowed
pic16(l)f1512/3 ds41624b-page 198 preliminary ? 2012 microchip technology inc. 20.4.9 acknowledge sequence the 9th scl pulse for any transferred byte in i 2 c is dedicated as an acknowledge. it allows receiving devices to respond back to the transmitter by pulling the sda line low. the transmitter must release control of the line during this time to shift in the response. the acknowledge (ack ) is an active-low signal, pulling the sda line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. the result of an ack is placed in the ackstat bit of the sspcon2 register. slave software, when the ahen and dhen bits are set, allow the user to set the ack value sent back to the transmitter. the ackdt bit of the sspcon2 register is set/cleared to determine the response. slave hardware will generate an ack response if the ahen and dhen bits of the sspcon3 register are clear. there are certain conditions where an ack will not be sent by the slave. if the bf bit of the sspstat register or the sspov bit of the sspcon1 register are set when a byte is received. when the module is addressed, after the 8th falling edge of scl on the bus, the acktim bit of the sspcon3 register is set. the acktim bit indicates the acknowledge time of the active bus. the acktim status bit is only active when the ahen bit or dhen bit is enabled. 20.5 i 2 c slave mode operation the mssp slave mode operates in one of four modes selected in the sspm bits of sspcon1 register. the modes can be divided into 7-bit and 10-bit addressing mode. 10-bit addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. modes with start and stop bit interrupts operate the same as the other modes with sspif additionally getting set upon detection of a start, restart, or stop condition. 20.5.1 slave mode addresses the sspadd register ( register 20-6 ) contains the slave mode address. the first byte received after a start or restart condition is compared against the value stored in this register. if the byte matches, the value is loaded into the sspbuf register and an interrupt is generated. if the value does not match, the module goes idle and no indication is given to the software that anything happened. the ssp mask register ( register 20-5 ) affects the address matching process. see section 20.5.9 ?ssp mask register? for more information. 20.5.1.1 i 2 c slave 7-bit addressing mode in 7-bit addressing mode, the lsb of the received data byte is ignored when determining if there is an address match. 20.5.1.2 i 2 c slave 10-bit addressing mode in 10-bit addressing mode, the first received byte is compared to the binary value of ?1 1 1 1 0 a9 a8 0?. a9 and a8 are the two msb of the 10-bit address and stored in bits 2 and 1 of the sspadd register. after the acknowledge of the high byte the ua bit is set and scl is held low until the user updates sspadd with the low address. the low address byte is clocked in and all 8 bits are compared to the low address value in sspadd. even if there is not an address match; sspif and ua are set, and scl is held low until sspadd is updated to receive a high byte again. when sspadd is updated the ua bit is cleared. this ensures the module is ready to receive the high address byte on the next communication. a high and low address match as a write request is required at the start of all 10-bit addressing communi- cation. a transmission can be initiated by issuing a restart once the slave is addressed, and clocking in the high address with the r/w bit set. the slave hardware will then acknowledge the read request and prepare to clock out data. this is only valid for a slave after it has received a complete high and low address byte match.
? 2012 microchip technology inc. preliminary ds41624b-page 199 pic16(l)f1512/3 20.5.2 slave reception when the r/w bit of a matching received address byte is clear, the r/w bit of the sspstat register is cleared. the received address is loaded into the sspbuf register and acknowledged. when the overflow condition exists for a received address, then not acknowledge is given. an overflow condition is defined as either bit bf bit of the sspstat register is set, or bit sspov bit of the sspcon1 register is set. the boen bit of the sspcon3 register modifies this operation. for more information see register 20-4 . an mssp interrupt is generated for each transferred data byte. flag bit, sspif, must be cleared by software. when the sen bit of the sspcon2 register is set, scl will be held low (clock stretch) following each received byte. the clock must be released by setting the ckp bit of the sspcon1 register, except sometimes in 10-bit mode. see section 20.2.3 ?spi master mode? for more detail. 20.5.2.1 7-bit addressing reception this section describes a standard sequence of events for the mssp module configured as an i 2 c slave in 7-bit addressing mode. figure 20-14 and figure 20-15 are used as visual references for this description. this is a step by step process of what typically must be done to accomplish i 2 c communication. 1. start bit detected. 2. s bit of sspstat is set; sspif is set if interrupt on start detect is enabled. 3. matching address with r/w bit clear is received. 4. the slave pulls sda low sending an ack to the master, and sets sspif bit. 5. software clears the sspif bit. 6. software reads received address from sspbuf clearing the bf flag. 7. if sen = 1 ; slave software sets ckp bit to release the scl line. 8. the master clocks out a data byte. 9. slave drives sda low sending an ack to the master, and sets sspif bit. 10. software clears sspif. 11. software reads the received byte from sspbuf clearing bf. 12. steps 8-12 are repeated for all received bytes from the master. 13. master sends stop condition, setting p bit of sspstat, and the bus goes idle. 20.5.2.2 7-bit reception with ahen and dhen slave device reception with ahen and dhen set operate the same as without these options with extra interrupts and clock stretching added after the 8th falling edge of scl. these additional interrupts allow the slave software to decide whether it wants to ack the receive address or data byte, rather than the hardware. this functionality adds support for pmbus? that was not present on previous versions of this module. this list describes the steps that need to be taken by slave software to use these options for i 2 c communi cation. figure 20-16 displays a module using both address and data holding. figure 20-17 includes the operation with the sen bit of the sspcon2 register set. 1. s bit of sspstat is set; sspif is set if interrupt on start detect is enabled. 2. matching address with r/w bit clear is clocked in. sspif is set and ckp cleared after the 8th falling edge of scl. 3. slave clears the sspif. 4. slave can look at the acktim bit of the sspcon3 register to determine if the sspif was after or before the ack. 5. slave reads the address value from sspbuf, clearing the bf flag. 6. slave sets ack value clocked out to the master by setting ackdt. 7. slave releases the clock by setting ckp. 8. sspif is set after an ack , not after a nack. 9. if sen = 1 the slave hardware will stretch the clock after the ack. 10. slave clears sspif. 11. sspif set and ckp cleared after 8th falling edge of scl for a received data byte. 12. slave looks at acktim bit of sspcon3 to determine the source of the interrupt. 13. slave reads the received data from sspbuf clearing bf. 14. steps 7-14 are the same for each received data byte. 15. communication is ended by either the slave sending an ack = 1 , or the master sending a stop condition. if a stop is sent and interrupt on stop detect is disabled, the slave will only know by polling the p bit of the sspstat register. note: sspif is still set after the 9th falling edge of scl even if there is no clock stretching and bf has been cleared. only if nack is sent to master is sspif not set
pic16(l)f1512/3 ds41624b-page 200 preliminary ? 2012 microchip technology inc. figure 20-14: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving data ack receiving data ack = 1 a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspif bf sspov 12345678 12345678 12345678 9 9 9 ack is not sent. sspov set because sspbuf is still full. cleared by software first byte of data is available in sspbuf sspbuf is read sspif set on 9th falling edge of scl cleared by software p bus master sends stop condition s from slave to master
? 2012 microchip technology inc. preliminary ds41624b-page 201 pic16(l)f1512/3 figure 20-15: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sen sen a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl 123456789 123456789 123456789 p sspif set on 9th scl is not held ckp is written to ? 1 ? in software, ckp is written to ? 1 ? in software, ack low because falling edge of scl releasing scl ack is not sent. bus master sends ckp sspov bf sspif sspov set because sspbuf is still full. cleared by software first byte of data is available in sspbuf ack = 1 cleared by software sspbuf is read clock is held low until ckp is set to ? 1 ? releasing scl stop condition s ack ack receive address receive data receive data r/w= 0
pic16(l)f1512/3 ds41624b-page 202 preliminary ? 2012 microchip technology inc. figure 20-16: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 1 , dhen = 1 ) receiving address receiving data received data p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl bf ckp s p 12 3 4 56 7 8 9 12345678 9 12345678 master sends stop condition s data is read from sspbuf cleared by software sspif is set on 9th falling edge of scl, after ack ckp set by software, scl is released slave software 9 acktim cleared by hardware in 9th rising edge of scl sets ackdt to not ack when dhen= 1 : ckp is cleared by hardware on 8th falling edge of scl slave software clears ackdt to ack the received byte acktim set by hardware on 8th falling edge of scl when ahen= 1 : ckp is cleared by hardware and scl is stretched address is read from ssbuf acktim set by hardware on 8th falling edge of scl ack master releases sda to slave for ack sequence no interrupt after not ack from slave ack = 1 ack ackdt acktim sspif if ahen = 1 : sspif is set
? 2012 microchip technology inc. preliminary ds41624b-page 203 pic16(l)f1512/3 figure 20-17: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 1 , dhen = 1 ) receiving address receive data receive data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspif bf ackdt ckp s p ack s 12 34 5678 9 12 3 4567 8 9 12 345 67 8 9 ack ack cleared by software acktim is cleared by hardware sspbuf can be set by software, read any time before next byte is loaded release scl on 9th rising edge of scl received address is loaded into sspbuf slave software clears ackdt to ack r/w = 0 master releases sda to slave for ack sequence the received byte when ahen = 1 ; on the 8th falling edge of scl of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of scl when dhen = 1 ; on the 8th falling edge of scl of a received data byte, ckp is cleared received data is available on sspbuf slave sends not ack ckp is not cleared if not ack p master sends stop condition no interrupt after if not ack from slave acktim
pic16(l)f1512/3 ds41624b-page 204 preliminary ? 2012 microchip technology inc. 20.5.3 slave transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspstat register is set. the received address is loaded into the sspbuf register, and an ack pulse is sent by the slave on the ninth bit. following the ack , slave hardware clears the ckp bit and the scl pin is held low (see section 20.5.6 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspbuf register which also loads the sspsr register. then the scl pin should be released by setting the ckp bit of the sspcon1 register. the eight data bits are shifted out on the falling edge of the scl input. this ensures that the sda signal is valid during the scl high time. the ack pulse from the master-receiver is latched on the rising edge of the ninth scl input pulse. this ack value is copied to the ackstat bit of the sspcon2 register. if ackstat is set (not ack ), then the data transfer is complete. in this case, when the not ack is latched by the slave, the slave goes idle and waits for another occurrence of the start bit. if the sda line was low (ack ), the next transmit data must be loaded into the sspbuf register. again, the scl pin must be released by setting bit ckp. an mssp interrupt is generated for each data transfer byte. the sspif bit must be cleared by software and the sspstat register is used to determine the status of the byte. the sspif bit is set on the falling edge of the ninth clock pulse. 20.5.3.1 slave mode bus collision a slave receives a read request and begins shifting data out on the sda line. if a bus collision is detected and the sbcde bit of the sspcon3 register is set, the bclif bit of the pir register is set. once a bus collision is detected, the slave goes idle and waits to be addressed again. user software can use the bclif bit to handle a slave bus collision. 20.5.3.2 7-bit transmission a master device can transmit a read request to a slave, and then clock data out of the slave. the list below outlines what software for a slave will need to do to accomplish a standard transmission. figure 20-17 can be used as a reference to this list. 1. master sends a start condition on sda and scl. 2. s bit of sspstat is set; sspif is set if interrupt on start detect is enabled. 3. matching address with r/w bit set is received by the slave setting sspif bit. 4. slave hardware generates an ack and sets sspif. 5. sspif bit is cleared by user. 6. software reads the received address from sspbuf, clearing bf. 7. r/w is set so ckp was automatically cleared after the ack. 8. the slave software loads the transmit data into sspbuf. 9. ckp bit is set releasing scl, allowing the master to clock the data out of the slave. 10. sspif is set after the ack response from the master is loaded into the ackstat register. 11. sspif bit is cleared. 12. the slave software checks the ackstat bit to see if the master wants to clock out more data. 13. steps 9-13 are repeated for each transmitted byte. 14. if the master sends a not ack ; the clock is not held, but sspif is still set. 15. the master sends a restart condition or a stop. 16. the slave is no longer addressed. note 1: if the master ack s the clock will be stretched. 2: ackstat is the only bit updated on the rising edge of scl (9th) rather than the falling.
? 2012 microchip technology inc. preliminary ds41624b-page 205 pic16(l)f1512/3 figure 20-18: i 2 c slave, 7-bit address, transmission (ahen = 0 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda scl sspif bf ckp ackstat r/w d/a s p received address when r/w is set r/w is copied from the indicates an address is read from sspbuf scl is always held low after 9th scl falling edge matching address byte has been received masters not ack is copied to ackstat ckp is not held for not ack bf is automatically cleared after 8th falling edge of scl data to transmit is loaded into sspbuf set by software cleared by software ack ack ack r/w = 1 s p master sends stop condition
pic16(l)f1512/3 ds41624b-page 206 preliminary ? 2012 microchip technology inc. 20.5.3.3 7-bit transmission with address hold enabled setting the ahen bit of the sspcon3 register enables additional clock stretching and interrupt generation after the 8th falling edge of a received matching address. once a matching address has been clocked in, ckp is cleared and the sspif interrupt is set. figure 20-18 displays a standard waveform of a 7-bit address slave transmission with ahen enabled. 1. bus starts idle. 2. master sends start condition; the s bit of sspstat is set; sspif is set if interrupt on start detect is enabled. 3. master sends matching address with r/w bit set. after the 8th falling edge of the scl line the ckp bit is cleared and sspif interrupt is generated. 4. slave software clears sspif. 5. slave software reads acktim bit of sspcon3 register, and r/w and d/a of the sspstat register to determine the source of the interrupt. 6. slave reads the address value from the sspbuf register clearing the bf bit. 7. slave software decides from this information if it wishes to ack or not ack and sets ackdt bit of the sspcon2 register accordingly. 8. slave sets the ckp bit releasing scl. 9. master clocks in the ack value from the slave. 10. slave hardware automatically clears the ckp bit and sets sspif after the ack if the r/w bit is set. 11. slave software clears sspif. 12. slave loads value to transmit to the master into sspbuf setting the bf bit. 13. slave sets ckp bit releasing the clock. 14. master clocks out the data from the slave and sends an ack value on the 9th scl pulse. 15. slave hardware copies the ack value into the ackstat bit of the sspcon2 register. 16. steps 10-15 are repeated for each byte transmitted to the master from the slave. 17. if the master sends a not ack the slave releases the bus allowing the master to send a stop and end the communication. note: sspbuf cannot be loaded until after the ack. note: master must send a not ack on the last byte to ensure that the slave releases the scl line to receive a stop.
? 2012 microchip technology inc. preliminary ds41624b-page 207 pic16(l)f1512/3 figure 20-19: i 2 c slave, 7-bit address, transmission (ahen = 1 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sda scl sspif bf ackdt ackstat ckp r/w d/a received address is read from sspbuf bf is automatically cleared after 8th falling edge of scl data to transmit is loaded into sspbuf cleared by software slave clears ackdt to ack address master?s ack response is copied to sspstat ckp not cleared after not ack set by software, releases scl acktim is cleared on 9th rising edge of scl acktim is set on 8th falling edge of scl when ahen = 1 ; ckp is cleared by hardware after receiving matching address. when r/w = 1 ; ckp is always cleared after ack s p master sends stop condition ack r/w = 1 master releases sda to slave for ack sequence ack ack acktim
pic16(l)f1512/3 ds41624b-page 208 preliminary ? 2012 microchip technology inc. 20.5.4 slave mode 10-bit address reception this section describes a standard sequence of events for the mssp module configured as an i 2 c slave in 10-bit addressing mode. figure 20-19 is used as a visual reference for this description. this is a step by step process of what must be done by slave software to accomplish i 2 c communication. 1. bus starts idle. 2. master sends start condition; s bit of sspstat is set; sspif is set if interrupt on start detect is enabled. 3. master sends matching high address with r/w bit clear; ua bit of the sspstat register is set. 4. slave sends ack and sspif is set. 5. software clears the sspif bit. 6. software reads received address from sspbuf clearing the bf flag. 7. slave loads low address into sspadd, releasing scl. 8. master sends matching low address byte to the slave; ua bit is set. 9. slave sends ack and sspif is set. 10. slave clears sspif. 11. slave reads the received matching address from sspbuf clearing bf. 12. slave loads high address into sspadd. 13. master clocks a data byte to the slave and clocks out the slaves ack on the 9th scl pulse; sspif is set. 14. if sen bit of sspcon2 is set, ckp is cleared by hardware and the clock is stretched. 15. slave clears sspif. 16. slave reads the received byte from sspbuf clearing bf. 17. if sen is set the slave sets ckp to release the scl. 18. steps 13-17 repeat for each received byte. 19. master sends stop to end the transmission. 20.5.5 10-bit addressing with address or data hold reception using 10-bit addressing with ahen or dhen set is the same as with 7-bit modes. the only difference is the need to update the sspadd register using the ua bit. all functionality, specifically when the ckp bit is cleared and scl line is held low are the same. figure 20-20 can be used as a reference of a slave in 10-bit addressing with ahen set. figure 20-21 shows a standard waveform for a slave transmitter in 10-bit addressing mode. note: updates to the sspadd register are not allowed until after the ack sequence. note: if the low address does not match, sspif and ua are still set so that the slave software can set sspadd back to the high address. bf is not set because there is no match. ckp is unaffected.
? 2012 microchip technology inc. preliminary ds41624b-page 209 pic16(l)f1512/3 figure 20-20: i 2 c slave, 10-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sspif receive first address byte ack receive second address byte ack receive data ack receive data ack 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sda scl ua ckp 1 2345678 912345678 912345678 9 12345678 9 p master sends stop condition cleared by software receive address is software updates sspadd data is read scl is held low set by software, while ckp = 0 from sspbuf releasing scl when sen = 1 ; ckp is cleared after 9th falling edge of received byte read from sspbuf and releases scl when ua = 1 ; if address matches set by hardware on 9th falling edge sspadd it is loaded into sspbuf scl is held low s bf
pic16(l)f1512/3 ds41624b-page 210 preliminary ? 2012 microchip technology inc. figure 20-21: i 2 c slave, 10-bit address, reception (sen = 0 , ahen = 1 , dhen = 0 ) receive first address byte ua receive second address byte ua receive data ack receive data 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 sda scl sspif bf ackdt ua ckp acktim 12345678 9 s ack ack 12 345678 9 12345678 91 2 sspbuf is read from received data sspbuf can be read anytime before the next received byte cleared by software falling edge of scl not allowed until 9th update to sspadd is set ckp with software releases scl scl clears ua and releases update of sspadd, set by hardware on 9th falling edge slave software clears ackdt to ack the received byte if when ahen = 1 ; on the 8th falling edge of scl of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of scl cleared by software r/w = 0
? 2012 microchip technology inc. preliminary ds41624b-page 211 pic16(l)f1512/3 figure 20-22: i 2 c slave, 10-bit address, transmission (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving second address byte sr receive first address byte ack transmitting data byte 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 1 1 1 0 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 sda scl sspif bf ua ckp r/w d/a 1 2345 6789 1 2345 6789 1 23 4 5 6789 1 23456 789 ack = 1 p master sends stop condition master sends not ack master sends restart event ack r/w = 0 s cleared by software after sspadd is updated, ua is cleared and scl is released high address is loaded received address is data to transmit is set by software indicates an address when r/w = 1 ; r/w is copied from the set by hardware ua indicates sspadd sspbuf loaded with received address must be updated has been received loaded into sspbuf releases scl masters not ack is copied matching address byte ckp is cleared on 9th falling edge of scl read from sspbuf back into sspadd ackstat set by hardware
pic16(l)f1512/3 ds41624b-page 212 preliminary ? 2012 microchip technology inc. 20.5.6 clock stretching clock stretching occurs when a device on the bus holds the scl line low effectively pausing communication. the slave may stretch the clock to allow more time to handle data or prepare a response for the master device. a master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. any stretching done by a slave is invisible to the master software and handled by the hardware that generates scl. the ckp bit of the sspcon1 register is used to control stretching in software. any time the ckp bit is cleared, the module will wait for the scl line to go low and then hold it. setting ckp will release scl and allow more communication. 20.5.6.1 normal clock stretching following an ack if the r/w bit of sspstat is set, a read request, the slave hardware will clear ckp. this allows the slave time to update sspbuf with data to transfer to the master. if the sen bit of sspcon2 is set, the slave hardware will always stretch the clock after the ack sequence. once the slave is ready; ckp is set by software and communication resumes. 20.5.6.2 10-bit addressing mode in 10-bit addressing mode, when the ua bit is set the clock is always stretched. this is the only time, the scl is stretched without ckp being cleared. scl is released immediately after a write to sspadd. 20.5.6.3 byte nacking when ahen bit of sspcon3 is set; ckp is cleared by hardware after the 8th falling edge of scl for a received matching address byte. when dhen bit of sspcon3 is set; ckp is cleared after the 8th falling edge of scl for received data. stretching after the 8th falling edge of scl allows the slave to look at the received address or data and decide if it wants to ack the received data. 20.5.7 clock synchronization and the ckp bit any time the ckp bit is cleared, the module will wait for the scl line to go low and then hold it. however, clearing the ckp bit will not assert the scl output low until the scl output is already sampled low. there- fore, the ckp bit will not assert the scl line until an external i 2 c master device has already asserted the scl line. the scl output will remain low until the ckp bit is set and all other devices on the i 2 c bus have released scl. this ensures that a write to the ckp bit will not violate the minimum high time requirement for scl (see figure 20-22 ). figure 20-23: clock synchronization timing note 1: the bf bit has no effect on if the clock will be stretched or not. this is different than previous versions of the module that would not stretch the clock, clear ckp, if sspbuf was read before the 9th falling edge of scl. 2: previous versions of the module did not stretch the clock for a transmission if sspbuf was loaded before the 9th falling edge of scl. it is now always cleared for read requests. note: previous versions of the module did not stretch the clock if the second address byte did not match. sda scl dx ? ? 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspcon1 ckp master device releases clock master device asserts clock
? 2012 microchip technology inc. preliminary ds41624b-page 213 pic16(l)f1512/3 20.5.8 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually determines which device will be the slave addressed by the master device. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is a reserved address in the i 2 c protocol, defined as address 0x00. when the gcen bit of the sspcon2 register is set, the slave module will automatically ack the reception of this address regardless of the value stored in sspadd. after the slave clocks in an address of all zeros with the r/w bit clear, an interrupt is generated and slave software can read sspbuf and respond. figure 20-23 shows a general call reception sequence. in 10-bit address mode, the ua bit will not be set on the reception of the general call address. the slave will prepare to receive the second byte as data, just as it would in 7-bit mode. if the ahen bit of the sspcon3 register is set, just as with any other address reception, the slave hardware will stretch the clock after the 8th falling edge of scl. the slave must then set its ackdt value and release the clock with communication progressing as it would normally. figure 20-24: slave mode general call address sequence 20.5.9 ssp mask register an ssp mask (sspmsk) register ( register 20-5 ) is available in i 2 c slave mode as a mask for the value held in the sspsr register during an address comparison operation. a zero (? 0 ?) bit in the sspmsk register has the effect of making the corresponding bit of the received address a ?don?t care?. this register is reset to all ? 1 ?s upon any reset condition and, therefore, has no effect on standard ssp operation until written with a mask value. the ssp mask register is active during: ? 7-bit address mode: address compare of a<7:1>. ? 10-bit address mode: address compare of a<7:0> only. the ssp mask has no effect during the reception of the first (high) byte of the address. sda scl s sspif bf (sspstat<0>) cleared by software sspbuf is read r/w = 0 ack general call address address is compared to general call address receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack , set interrupt gcen (sspcon2<7>) ? 1 ?
pic16(l)f1512/3 ds41624b-page 214 preliminary ? 2012 microchip technology inc. 20.6 i 2 c master mode master mode is enabled by setting and clearing the appropriate sspm bits in the sspcon1 register and by setting the sspen bit. in master mode, the sda and sck pins must be configured as inputs. the mssp peripheral hardware will override the output driver tris controls when necessary to drive the pins low. master mode of operation is supported by interrupt generation on the detection of the start and stop conditions. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit is set, or the bus is idle. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit condition detection. start and stop condition detection is the only active circuitry in this mode. all other communication is done by the user software directly manipulating the sda and scl lines. the following events will cause the ssp interrupt flag bit, sspif, to be set (ssp interrupt, if enabled): ? start condition detected ? stop condition detected ? data transfer byte transmitted/received ? acknowledge transmitted/received ? repeated start generated 20.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sda, while scl outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (7 bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted eight bits at a time. after each byte is transmitted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted contains the slave address of the transmitting device (7 bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate the receive bit. serial data is received via sda, while scl outputs the serial clock. serial data is received eight bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmission. a baud rate generator is used to set the clock frequency output on scl. see section 20.7 ?baud rate generator? for more detail. note 1: the mssp module, when configured in i 2 c master mode, does not allow queueing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspbuf register to initiate transmission before the start condition is complete. in this case, the sspbuf will not be written to and the wcol bit will be set, indicating that a write to the sspbuf did not occur 2: when in master mode, start/stop detection is masked and an interrupt is generated when the sen/pen bit is cleared and the generation is complete.
? 2012 microchip technology inc. preliminary ds41624b-page 215 pic16(l)f1512/3 20.6.2 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, releases the scl pin (scl allowed to float high). when the scl pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the scl pin is actually sampled high. when the scl pin is sampled high, the baud rate generator is reloaded with the contents of sspadd<7:0> and begins counting. this ensures that the scl high time will always be at least one brg rollover count in the event that the clock is held low by an external device ( figure 20-25 ). figure 20-25: baud rate generator timing with clock arbitration 20.6.3 wcol status flag if the user writes the sspbuf when a start, restart, stop, receive or transmit sequence is in progress, the wcol is set and the contents of the buffer are unchanged (the write does not occur). any time the wcol bit is set it indicates that an action on sspbuf was attempted while the module was not idle. sda scl scl deasserted but slave holds dx ? ? 1 dx brg scl is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value scl low (clock arbitration) scl allowed to transition high brg decrements on q2 and q4 cycles note: because queueing of events is not allowed, writing to the lower five bits of sspcon2 is disabled until the start condition is complete.
pic16(l)f1512/3 ds41624b-page 216 preliminary ? 2012 microchip technology inc. 20.6.4 i 2 c master mode start condition timing to initiate a start condition, the user sets the start enable bit, sen bit of the sspcon2 register. if the sda and scl pins are sampled high, the baud rate generator is reloaded with the contents of sspadd<7:0> and starts its count. if scl and sda are both sampled high when the baud rate generator times out (t brg ), the sda pin is driven low. the action of the sda being driven low while scl is high is the start condition and causes the s bit of the sspstat1 register to be set. following this, the baud rate generator is reloaded with the contents of sspadd<7:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit of the sspcon2 register will be automatically cleared by hardware; the baud rate generator is suspended, leaving the sda line held low and the start condition is complete. figure 20-26: first start bit timing note 1: if at the beginning of the start condition, the sda and scl pins are already sampled low, or if during the start condition, the scl line is sampled low before the sda line is driven low, a bus collision occurs, the bus collision interrupt flag, bclif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. 2: the philips i 2 c specification states that a bus collision cannot occur on a start. sda scl s t brg 1st bit 2nd bit t brg sda = 1 , at completion of start bit, scl = 1 write to sspbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspstat<3>) and sets sspif bit
? 2012 microchip technology inc. preliminary ds41624b-page 217 pic16(l)f1512/3 20.6.5 i 2 c master mode repeated start condition timing a repeated start condition occurs when the rsen bit of the sspcon2 register is programmed high and the master state machine is no longer active. when the rsen bit is set, the scl pin is asserted low. when the scl pin is sampled low, the baud rate generator is loaded and begins counting. the sda pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sda is sampled high, the scl pin will be deasserted (brought high). when scl is sampled high, the baud rate generator is reloaded and begins counting. sda and scl must be sampled high for one t brg . this action is then followed by assertion of the sda pin (sda = 0 ) for one t brg while scl is high. scl is asserted low. following this, the rsen bit of the sspcon2 register will be automatically cleared and the baud rate generator will not be reloaded, leaving the sda pin held low. as soon as a start condition is detected on the sda and scl pins, the s bit of the sspstat register will be set. the sspif bit will not be set until the baud rate generator has timed out. figure 20-27: repeat start condition waveform 20.6.6 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the sspbuf register. this action will set the buffer full flag bit, bf and allow the baud rate generator to begin counting and start the next trans- mission. each bit of address/data will be shifted out onto the sda pin after the falling edge of scl is asserted. scl is held low for one baud rate generator rollover count (t brg ). data should be valid before scl is released high. when the scl pin is released high, it is held that way for t brg . the data on the sda pin must remain stable for that duration and some hold time after the next falling edge of scl. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sda. this allows the slave device being addressed to respond with an ack bit during the ninth bit time if an address match occurred, or if data was received prop- erly. the status of ack is written into the ackstat bit on the rising edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the sspif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspbuf, leaving scl low and sda unchanged ( figure 20-27 ). after the write to the sspbuf, each bit of the address will be shifted out on the falling edge of scl until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock, the master will release the sda pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sda pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit of the sspcon2 register. following the falling edge of the ninth clock transmission of the address, the sspif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspbuf takes place, holding scl low and allowing sda to float. note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: ? sda is sampled low when scl goes from low-to-high. ? scl goes low before sda is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. sda scl repeated start write to sspcon2 write to sspbuf occurs here at completion of start bit, hardware clears rsen bit 1st bit s bit set by hardware t brg t brg sda = 1 , sda = 1 , scl (no change) scl = 1 occurs here t brg t brg t brg and sets sspif sr
pic16(l)f1512/3 ds41624b-page 218 preliminary ? 2012 microchip technology inc. 20.6.6.1 bf status flag in transmit mode, the bf bit of the sspstat register is set when the cpu writes to sspbuf and is cleared when all 8 bits are shifted out. 20.6.6.2 wcol status flag if the user writes the sspbuf when a transmit is already in progress (i.e., sspsr is still shifting out a data byte), the wcol is set and the contents of the buffer are unchanged (the write does not occur). wcol must be cleared by software before the next transmission. 20.6.6.3 ackstat status flag in transmit mode, the ackstat bit of the sspcon2 register is cleared when the slave has sent an acknowledge (ack = 0 ) and is set when the slave does not acknowledge (ack = 1 ). a slave sends an acknowledge when it has recognized its address (including a general call), or when the slave has properly received its data. 20.6.6.4 typical transmit sequence: 1. the user generates a start condition by setting the sen bit of the sspcon2 register. 2. sspif is set by hardware on completion of the start. 3. sspif is cleared by software. 4. the mssp module will wait the required start time before any other operation takes place. 5. the user loads the sspbuf with the slave address to transmit. 6. address is shifted out the sda pin until all eight bits are transmitted. transmission begins as soon as sspbuf is written to. 7. the mssp module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspcon2 register. 8. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 9. the user loads the sspbuf with eight bits of data. 10. data is shifted out the sda pin until all eight bits are transmitted. 11. the mssp module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspcon2 register. 12. steps 8-11 are repeated for all transmitted data bytes. 13. the user generates a stop or restart condition by setting the pen or rsen bits of the sspcon2 register. interrupt is generated once the stop/restart condition is complete.
? 2012 microchip technology inc. preliminary ds41624b-page 219 pic16(l)f1512/3 figure 20-28: i 2 c master mode waveform (transmission, 7 or 10-bit address) sda scl sspif bf (sspstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared by software service routine sspbuf is written by software from ssp interrupt after start condition, sen cleared by hardware s sspbuf written with 7-bit address and r/w start transmit scl held low while cpu responds to sspif sen = 0 of 10-bit address write sspcon2<0> sen = 1 start condition begins from slave, clear ackstat bit sspcon2<6> ackstat in sspcon2 = 1 cleared by software sspbuf written pen r/w cleared by software
pic16(l)f1512/3 ds41624b-page 220 preliminary ? 2012 microchip technology inc. 20.6.7 i 2 c master mode reception master mode reception is enabled by programming the receive enable bit, rcen bit of the sspcon2 register. the baud rate generator begins counting and on each rollover, the state of the scl pin changes (high-to-low/low-to-high) and data is shifted into the sspsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the contents of the sspsr are loaded into the sspbuf, the bf flag bit is set, the sspif flag bit is set and the baud rate generator is suspended from counting, holding scl low. the mssp is now in idle state awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable, acken bit of the sspcon2 register. 20.6.7.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspbuf from sspsr. it is cleared when the sspbuf register is read. 20.6.7.2 sspov status flag in receive operation, the sspov bit is set when eight bits are received into the sspsr and the bf flag bit is already set from a previous reception. 20.6.7.3 wcol status flag if the user writes the sspbuf when a receive is already in progress (i.e., sspsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). 20.6.7.4 typical receive sequence: 1. the user generates a start condition by setting the sen bit of the sspcon2 register. 2. sspif is set by hardware on completion of the start. 3. sspif is cleared by software. 4. user writes sspbuf with the slave address to transmit and the r/w bit set. 5. address is shifted out the sda pin until all eight bits are transmitted. transmission begins as soon as sspbuf is written to. 6. the mssp module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspcon2 register. 7. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspif bit. 8. user sets the rcen bit of the sspcon2 register and the master clocks in a byte from the slave. 9. after the 8th falling edge of scl, sspif and bf are set. 10. master clears sspif and reads the received byte from sspuf, clears bf. 11. master sets ack value sent to slave in ackdt bit of the sspcon2 register and initiates the ack by setting the acken bit. 12. masters ack is clocked out to the slave and sspif is set. 13. user clears sspif. 14. steps 8-13 are repeated for each received byte from the slave. 15. master sends a not ack or stop to end communication. note: the mssp module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded.
? 2012 microchip technology inc. preliminary ds41624b-page 221 pic16(l)f1512/3 figure 20-29: i 2 c master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sda scl 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w transmit address to slave sspif bf ack is not sent write to sspcon2<0> (sen = 1 ), write to sspbuf occurs here, ack from slave master configured as a receiver by programming sspcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared by software start xmit sen = 0 sspov sda = 0 , scl = 1 while cpu (sspstat<0>) ack cleared by software cleared by software set sspif interrupt at end of receive set p bit (sspstat<4>) and sspif cleared in software ack from master set sspif at end set sspif interrupt at end of acknowledge sequence set sspif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence sspov is set because sspbuf is still full sda = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspcon2<4> to start acknowledge sequence sda = ackdt (sspcon2<5>) = 0 rcen cleared automatically responds to sspif acken begin start condition cleared by software sda = ackdt = 0 last bit is shifted into sspsr and contents are unloaded into sspbuf rcen master configured as a receiver by programming sspcon2<3> (rcen = 1 ) rcen cleared automatically ack from master sda = ackdt = 0 rcen cleared automatically
pic16(l)f1512/3 ds41624b-page 222 preliminary ? 2012 microchip technology inc. 20.6.8 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken bit of the sspcon2 register. when this bit is set, the scl pin is pulled low and the contents of the acknowledge data bit are presented on the sda pin. if the user wishes to generate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the scl pin is deasserted (pulled high). when the scl pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the scl pin is then pulled low. following this, the acken bit is automatically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode ( figure 20-29 ). 20.6.8.1 wcol status flag if the user writes the sspbuf when an acknowledge sequence is in progress, then wcol is set and the contents of the buffer are unchanged (the write does not occur). 20.6.9 stop condition timing a stop bit is asserted on the sda pin at the end of a receive/transmit by setting the stop sequence enable bit, pen bit of the sspcon2 register. at the end of a receive/transmit, the scl line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sda line low. when the sda line is sampled low, the baud rate generator is reloaded and counts down to ? 0 ?. when the baud rate generator times out, the scl pin will be brought high and one t brg (baud rate generator rollover count) later, the sda pin will be deasserted. when the sda pin is sampled high while scl is high, the p bit of the sspstat register is set. a t brg later, the pen bit is cleared and the sspif bit is set ( figure 20-30 ). 20.6.9.1 wcol status flag if the user writes the sspbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). figure 20-30: acknowledge sequen ce waveform note: t brg = one baud rate generator period. sda scl sspif set at acknowledge sequence starts here, write to sspcon2 acken automatically cleared cleared in t brg t brg the end of receive 8 acken = 1 , ackdt = 0 d0 9 sspif software sspif set at the end of acknowledge sequence cleared in software ack
? 2012 microchip technology inc. preliminary ds41624b-page 223 pic16(l)f1512/3 figure 20-31: stop cond ition receive or transmit mode 20.6.10 sleep operation while in sleep mode, the i 2 c slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 20.6.11 effects of a reset a reset disables the mssp module and terminates the current transfer. 20.6.12 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit of the sspstat register is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will gener- ate the interrupt when the stop condition occurs. in multi-master operation, the sda line must be monitored for arbitration to see if the signal level is the expected output level. this check is performed by hardware with the result placed in the bclif bit. the states where arbitration can be lost are: ? address transfer ? data transfer ? a start condition ? a repeated start condition ? an acknowledge condition 20.6.13 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sda pin, arbitration takes place when the master outputs a ? 1 ? on sda, by letting sda float high and another master asserts a ? 0 ?. when the scl pin floats high, data should be stable. if the expected data on sda is a ? 1 ? and the data sampled on the sda pin is ? 0 ?, then a bus collision has taken place. the master will set the bus collision interrupt flag, bclif and reset the i 2 c port to its idle state ( figure 20-31 ). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sda and scl lines are deasserted and the sspbuf can be written to. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. if a start, repeated start, stop or acknowledge condition was in progress when the bus collision occurred, the condition is aborted, the sda and scl lines are deasserted and the respective control bits in the sspcon2 register are cleared. when the user services the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sda and scl pins. if a stop condition occurs, the sspif bit will be set. a write to the sspbuf will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the determination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspstat register, or the bus is idle and the s and p bits are cleared. scl sda sda asserted low before rising edge of clock write to sspcon2, set pen falling edge of scl = 1 for t brg , followed by sda = 1 for t brg 9th clock scl brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sda sampled high. p bit (sspstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspcon2<2>) is cleared by hardware and the sspif bit is set
pic16(l)f1512/3 ds41624b-page 224 preliminary ? 2012 microchip technology inc. figure 20-32: bus collision timing for transmit and acknowledge sda scl bclif sda released sda line pulled low by another source sample sda. while scl is high, data does not match what is driven bus collision has occurred. set bus collision interrupt (bclif) by the master. by master data changes while scl = 0
? 2012 microchip technology inc. preliminary ds41624b-page 225 pic16(l)f1512/3 20.6.13.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition ( figure 20-32 ). b) scl is sampled low before sda is asserted low ( figure 20-33 ). during a start condition, both the sda and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: ? the start condition is aborted, ? the bclif flag is set and ? the mssp module is reset to its idle state ( figure 20-32 ). the start condition begins with the sda and scl pins deasserted. when the sda pin is sampled high, the baud rate generator is loaded and counts down. if the scl pin is sampled low while sda is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sda pin is sampled low during this count, the brg is reset and the sda line is asserted early ( figure 20-34 ). if, however, a ? 1 ? is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to zero; if the scl pin is sampled as ? 0 ? during this time, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 20-33: bus collision during start condition (sda only) note: the reason that bus collision is not a factor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sda before the other. this condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address following the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sda scl sen sda sampled low before sda goes low before the sen bit is set. s bit and sspif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspif set because set sen, enable start condition if sda = 1 , scl = 1 sda = 0 , scl = 1 . bclif s sspif sda = 0 , scl = 1 . sspif and bclif are cleared by software sspif and bclif are cleared by software set bclif, start condition. set bclif.
pic16(l)f1512/3 ds41624b-page 226 preliminary ? 2012 microchip technology inc. figure 20-34: bus collision d uring start condition (scl = 0 ) figure 20-35: brg reset due to sda arbitration during start condition sda scl sen bus collision occurs. set bclif. scl = 0 before sda = 0 , set sen, enable start sequence if sda = 1 , scl = 1 t brg t brg sda = 0 , scl = 1 bclif s sspif interrupt cleared by software bus collision occurs. set bclif. scl = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sda scl sen set s less than t brg t brg sda = 0 , scl = 1 bclif s sspif s interrupts cleared by software set sspif sda = 0 , scl = 1 , scl pulled low after brg time-out set sspif ? 0 ? sda pulled low by other master. reset brg and assert sda. set sen, enable start sequence if sda = 1 , scl = 1
? 2012 microchip technology inc. preliminary ds41624b-page 227 pic16(l)f1512/3 20.6.13.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sda when scl goes from low level to high level. b) scl goes low before sda is asserted low, indicating that another master is attempting to transmit a data ? 1 ?. when the user releases sda and the pin is allowed to float high, the brg is loaded with sspadd and counts down to zero. the scl pin is then deasserted and when sampled high, the sda pin is sampled. if sda is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, figure 20-35 ). if sda is sampled high, the brg is reloaded and begins counting. if sda goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sda at exactly the same time. if scl goes from high-to-low before the brg times out and sda has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition, see figure 20-36 . if, at the end of the brg time-out, both scl and sda are still high, the sda pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the scl pin, the scl pin is driven low and the repeated start condition is complete. figure 20-36: bus collision during a repeat ed start condition (case 1) figure 20-37: bus collision during repeat ed start condition (case 2) sda scl rsen bclif s sspif sample sda when scl goes high. if sda = 0 , set bclif and release sda and scl. cleared by software ? 0 ? ? 0 ? sda scl bclif rsen s sspif interrupt cleared by software scl goes low before sda, set bclif. release sda and scl. t brg t brg ? 0 ?
pic16(l)f1512/3 ds41624b-page 228 preliminary ? 2012 microchip technology inc. 20.6.13.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sda pin has been deasserted and allowed to float high, sda is sampled low after the brg has timed out. b) after the scl pin is deasserted, scl is sampled low before sda goes high. the stop condition begins with sda asserted low. when sda is sampled low, the scl pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspadd and counts down to zero. after the brg times out, sda is sampled. if sda is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? ( figure 20-37 ). if the scl pin is sampled low before sda is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data ? 0 ? ( figure 20-38 ). figure 20-38: bus collision during a stop condition (case 1) figure 20-39: bus collision during a stop condition (case 2) sda scl bclif pen p sspif t brg t brg t brg sda asserted low sda sampled low after t brg , set bclif ? 0 ? ? 0 ? sda scl bclif pen p sspif t brg t brg t brg assert sda scl goes low before sda goes high, set bclif ? 0 ? ? 0 ?
? 2012 microchip technology inc. preliminary ds41624b-page 229 pic16(l)f1512/3 table 20-3: summary of registers associated with i 2 c? operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pie2 osfie ? ? ?bclie ? ? ccp2ie 74 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 pir2 osfif ? ? ? bclif ? ? ccp2if 76 sspadd add<7:0> 235 sspbuf synchronous serial port receive buffer/transmit register 187 * sspcon1 wcol sspov sspen ckp sspm<3:0> 232 sspcon2 gcen ackstat ackdt acken rcen pen rsen sen 233 sspcon3 acktim pcie scie boen sdaht sbcde ahen dhen 234 sspmsk msk7 msk6 msk5 msk4 msk3 msk2 msk1 msk0 235 sspstat smp cke d/a p s r/w ua bf 231 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 108 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the mssp module in i 2 c? mode. * page provides register information.
pic16(l)f1512/3 ds41624b-page 230 preliminary ? 2012 microchip technology inc. 20.7 baud rate generator the mssp module has a baud rate generator available for clock generation in both i 2 c and spi master modes. the baud rate generator (brg) reload value is placed in the sspadd register ( register 20-6 ). when a write occurs to sspbuf, the baud rate generator will automatically begin counting down. once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. an internal signal ?reload? in figure 20-39 triggers the value from sspadd to be loaded into the brg counter. this occurs twice for each oscillation of the module clock line. the logic dictating when the reload signal is asserted depends on the mode the mssp is being operated in. table 20-4 demonstrates clock rates based on instruction cycles and the brg value loaded into sspadd. equation 20-1: figure 20-40: baud rate genera tor block diagram table 20-4: mssp clock rate w/brg f clock f osc sspadd 1 + ?? 4 ?? ---------------------------------------------- = note: values of 0x00, 0x01 and 0x02 are not valid for sspadd when used as a baud rate generator for i 2 c. this is an implementation limitation. f osc f cy brg value f clock (2 rollovers of brg) 16 mhz 4 mhz 09h 400 khz (1) 16 mhz 4 mhz 0ch 308 khz 16 mhz 4 mhz 27h 100 khz 4 mhz 1 mhz 09h 100 khz note 1: the i 2 c interface does not conform to the 400 khz i 2 c specification (which applies to rates greater than 100 khz) in all details, but may be used with care where higher rates are required by the application. sspm<3:0> brg down counter sspclk f osc /2 sspadd<7:0> sspm<3:0> scl reload control reload
? 2012 microchip technology inc. preliminary ds41624b-page 231 pic16(l)f1512/3 20.8 mssp control registers register 20-1: sspstat: ssp status register r/w-0/0 r/w-0/0 r-0/0 r-0/0 r-0/0 r-0/0 r-0/0 r-0/0 smp cke d/a psr/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 smp: spi data input sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode in i 2 c master or slave mode: 1 = slew rate control disabled for standard speed mode (100 khz and 1 mhz) 0 = slew rate control enabled for high speed mode (400 khz) bit 6 cke: spi clock edge select bit (spi mode only) in spi master or slave mode: 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state in i 2 c ? mode only: 1 = enable input logic so that thresholds are compliant with smbus specification 0 = disable smbus specific inputs bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (i 2 c mode only. this bit is cleared when the ms sp module is disabled, sspen is cleared.) 1 = indicates that a stop bit has been detected last (this bit is ? 0 ? on reset) 0 = stop bit was not detected last bit 3 s: start bit (i 2 c mode only. this bit is cleared when the ms sp module is disabled, sspen is cleared.) 1 = indicates that a start bit has been detected last (this bit is ? 0 ? on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not ack bit. in i 2 c slave mode: 1 = read 0 =write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress or-ing this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in idle mode. bit 1 ua: update address bit (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspadd register 0 = address does not need to be updated bit 0 bf: buffer full status bit receive (spi and i 2 c modes): 1 = receive complete, sspbuf is full 0 = receive not complete, sspbuf is empty transmit (i 2 c mode only): 1 = data transmit in progress (does not include the ack and stop bits), sspbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspbuf is empty
pic16(l)f1512/3 ds41624b-page 232 preliminary ? 2012 microchip technology inc. register 20-2: sspcon1: ssp control register 1 r/c/hs-0/0 r/c/hs-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 wcol sspov sspen ckp sspm<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hs = bit is set by hardware c = user cleared bit 7 wcol: write collision detect bit master mode: 1 = a write to the sspbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision slave mode: 1 = the sspbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit (1) in spi mode: 1 = a new byte is received while the sspbuf register is still holding the previous data. in case of overflow, the data in sspsr i s lost. overflow can only occur in slave mode. in slave mode, the user must read the sspbu f, even if only transmitting data, to avoid setting overflow. in master mode, the overflow bit is not set si nce each new reception (and transmission) is initiated by writi ng to the sspbuf register (must be cleared in software). 0 = no overflow in i 2 c mode: 1 = a byte is received while the sspbuf register is still holding the previous byte. sspov is a ?don?t care? in transmit mode (must be cleared in software). 0 = no overflow bit 5 sspen: synchronous serial port enable bit in both modes, when enabled, these pins must be properly configured as input or output in spi mode: 1 = enables serial port and configures sck, sdo, sdi and ss as the source of the serial port pins (2) 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and configures the sda and scl pins as the source of the serial port pins (3) 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: clock polarity select bit in spi mode: 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c slave mode: scl release control 1 = enable clock 0 = holds clock low (clock stretch). (used to ensure data setup time.) in i 2 c master mode: unused in this mode bit 3-0 sspm<3:0>: synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = tmr2 output/2 0100 = spi slave mode, clock = sck pin, ss pin control enabled 0101 = spi slave mode, clock = sck pin, ss pin control disabled, ss can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = i 2 c master mode, clock = f osc / (4 * (sspadd+1)) (4) 1001 = reserved 1010 = spi master mode, clock = f osc /(4 * (sspadd+1)) (5) 1011 = i 2 c firmware controlled master mode (slave idle) 1100 = reserved 1101 = reserved 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with start and stop bit interrupts enabled note 1: in master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the sspbuf r egister. 2: when enabled, these pins must be properly configured as input or output. 3: when enabled, the sda and scl pins must be configured as inputs. 4: sspadd values of 0, 1 or 2 are not supported for i 2 c mode. 5: sspadd value of ? 0 ? is not supported. use sspm = 0000 instead.
? 2012 microchip technology inc. preliminary ds41624b-page 233 pic16(l)f1512/3 register 20-3: sspcon2: ssp control register 2 r/w-0/0 r-0/0 r/w-0/0 r/s/hs-0/0 r/s/hs- 0/0 r/s/hs-0/0 r/s/hs-0/0 r/w/hs-0/0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hc = cleared by hardware s = user set bit 7 gcen: general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0x00 or 00h) is received in the sspsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (in i 2 c mode only) 1 = acknowledge was not received 0 = acknowledge was received bit 5 ackdt: acknowledge data bit (in i 2 c mode only) in receive mode: value transmitted when the user initiates an acknowledge sequence at the end of a receive 1 = not acknowledge 0 = acknowledge bit 4 acken: acknowledge sequence enable bit (in i 2 c master mode only) in master receive mode: 1 = initiate acknowledge sequence on sda and scl pins, and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (in i 2 c master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (in i 2 c master mode only) sckmssp release control: 1 = initiate stop condition on sda and scl pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enabled bit (in i 2 c master mode only) 1 = initiate repeated start condition on sda and scl pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enabled bit (in i 2 c master mode only) in master mode: 1 = initiate start condition on sda and scl pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note 1: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspbuf may not be written (or writes to the sspbuf are disabled).
pic16(l)f1512/3 ds41624b-page 234 preliminary ? 2012 microchip technology inc. register 20-4: sspcon3: ssp control register 3 r-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 acktim pcie scie boen sdaht sbcde ahen dhen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 acktim: acknowledge time status bit (i 2 c mode only) (3) 1 = indicates the i 2 c bus is in an acknowledge sequence, set on 8 th falling edge of scl clock 0 = not an acknowledge sequence, cleared on 9 th rising edge of scl clock bit 6 pcie : stop condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of stop condition 0 = stop detection interrupts are disabled (2) bit 5 scie : start condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of start or restart conditions 0 = start detection interrupts are disabled (2) bit 4 boen: buffer overwrite enable bit in spi slave mode: (1) 1 = sspbuf updates every time that a new data byte is shifted in ignoring the bf bit 0 = if new byte is received with bf bit of the sspstat register already set, sspov bit of the sspcon1 register is set, and the buffer is not updated in i 2 c master mode and spi master mode: this bit is ignored. in i 2 c slave mode: 1 = sspbuf is updated and ack is generated for a received address/data byte, ignoring the state of the sspov bit only if the bf bit = 0 . 0 = sspbuf is only updated when sspov is clear bit 3 sdaht: sda hold time selection bit (i 2 c mode only) 1 = minimum of 300 ns hold time on sda after the falling edge of scl 0 = minimum of 100 ns hold time on sda after the falling edge of scl bit 2 sbcde: slave mode bus collision detect enable bit (i 2 c slave mode only) if on the rising edge of scl, sda is sampled low when the module is outputting a high state, the bclif bit of the pir2 register is set, and bus goes idle 1 = enable slave bus collision interrupts 0 = slave bus collision interrupts are disabled bit 1 ahen: address hold enable bit (i 2 c slave mode only) 1 = following the 8th falling edge of scl for a matching received address byte; ckp bit of the sspcon1 register will be cleared and the scl will be held low. 0 = address holding is disabled bit 0 dhen: data hold enable bit (i 2 c slave mode only) 1 = following the 8th falling edge of scl for a received data byte; slave hardware clears the ckp bit of the sspcon1 register and scl is held low. 0 = data holding is disabled note 1: for daisy-chained spi operation; allows the user to ignore all but the last received byte. sspov is still set when a new byte is received and bf = 1 , but hardware continues to write the most recent byte to sspbuf. 2: this bit has no effect in slave modes that start and stop condition detection is explicitly listed as enabled. 3: the acktim status bit is only active when the ahen bit or dhen bit is set.
? 2012 microchip technology inc. preliminary ds41624b-page 235 pic16(l)f1512/3 register 20-5: sspmsk: ssp mask register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 msk<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-1 msk<7:1>: mask bits 1 = the received address bit n is compared to sspadd to detect i 2 c address match 0 = the received address bit n is not used to detect i 2 c address match bit 0 msk<0>: mask bit for i 2 c slave mode, 10-bit address i 2 c slave mode, 10-bit address (sspm<3:0> = 0111 or 1111 ) : 1 = the received address bit 0 is compared to sspadd<0> to detect i 2 c address match 0 = the received address bit 0 is not used to detect i 2 c address match i 2 c slave mode, 7-bit address : the bit is ignored. register 20-6: sspadd: mssp address and baud rate register (i 2 c mode) r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 add<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared master mode: bit 7-0 add<7:0>: baud rate clock divider bits scl pin clock period = ((add<7:0> + 1) *4)/f osc 10-bit slave mode ? most significant address byte: bit 7-3 not used: unused for most significant address byte. bit state of this register is a ?don?t care?. bit pat- tern sent by master is fixed by i 2 c specification and must be equal to ? 11110 ?. however, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 add<2:1>: two most significant bits of 10-bit address bit 0 not used: unused in this mode. bit state is a ?don?t care?. 10-bit slave mode ? least significant address byte: bit 7-0 add<7:0>: eight least significant bits of 10-bit address 7-bit slave mode: bit 7-1 add<7:1>: 7-bit address bit 0 not used: unused in this mode. bit state is a ?don?t care?.
pic16(l)f1512/3 ds41624b-page 236 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds41624b-page 237 pic16(l)f1512/3 21.0 capture/compare/pwm modules the capture/compare/pwm module is a peripheral which allows the user to time and control different events, and to generate pulse-width modulation (pwm) signals. in capture mode, the peripheral allows the timing of the duration of an event. the compare mode allows the user to trigger an external event when a predetermined amount of time has expired. the pwm mode can generate pulse-width modulated signals of varying frequency and duty cycle. this family of devices contains two standard capture/ compare/pwm modules (ccp1 and ccp2). the capture and compare functions are identical for all ccp modules. note 1: in devices with more than one ccp module, it is very important to pay close attention to the register names used. a number placed after the module acronym is used to distinguish between separate modules. for example, the ccp1con and ccp2con control the same operational aspects of two completely different ccp modules. 2: throughout this section, generic references to a ccp module in any of its operating modes may be interpreted as being equally applicable to ccpx module. register names, module signals, i/o pins, and bit names may use the generic designator ?x? to indicate the use of a numeral to distinguish a particular module, when required.
pic16(l)f1512/3 ds41624b-page 238 preliminary ? 2012 microchip technology inc. 21.1 capture mode the capture mode function described in this section is available and identical for all ccp modules. capture mode makes use of the 16-bit timer1 resource. when an event occurs on the ccpx pin, the 16-bit ccprxh:ccprxl register pair captures and stores the 16-bit value of the tmr1h:tmr1l register pair, respectively. an event is defined as one of the following and is configured by the ccpxm<3:0> bits of the ccpxcon register: ? every falling edge ? every rising edge ? every 4th rising edge ? every 16th rising edge when a capture is made, the interrupt request flag bit ccpxif of the pirx register is set. the interrupt flag must be cleared in software. if another capture occurs before the value in the ccprxh, ccprxl register pair is read, the old captured value is overwritten by the new captured value. figure 21-1 shows a simplified diagram of the capture operation. 21.1.1 ccp pin configuration in capture mode, the ccpx pin should be configured as an input by setting the associated tris control bit. also, the ccp2 pin function can be moved to alternative pins using the apfcon register. refer to section register 12-1: ?apfcon: alternate pin function control register? for more details. figure 21-1: capture mode operation block diagram 21.1.2 timer1 mode resource timer1 must be running in timer mode or synchronized counter mode for the ccp module to use the capture feature. in asynchronous counter mode, the capture operation may not work. see section 18.0 ?timer1 module with gate control? for more information on configuring timer1. 21.1.3 software interrupt mode when the capture mode is changed, a false capture interrupt may be generated. the user should keep the ccpxie interrupt enable bit of the piex register clear to avoid false interrupts. additionally, the user should clear the ccpxif interrupt flag bit of the pirx register following any change in operating mode. 21.1.4 ccp prescaler there are four prescaler settings specified by the ccpxm<3:0> bits of the ccpxcon register. whenever the ccp module is turned off, or the ccp module is not in capture mode, the prescaler counter is cleared. any reset will clear the prescaler counter. switching from one capture prescaler to another does not clear the prescaler and may generate a false interrupt. to avoid this unexpected operation, turn the module off by clearing the ccpxcon register before changing the prescaler. equation 21-1 demonstrates the code to perform this function. example 21-1: changing between capture prescalers note: if the ccpx pin is configured as an output, a write to the port can cause a capture condition. ccprxh ccprxl tmr1h tmr1l set flag bit ccpxif (pirx register) capture enable ccpxm<3:0> prescaler ? 1, 4, 16 and edge detect pin ccpx system clock (f osc ) banksel ccpxcon ;set bank bits to point ;to ccpxcon clrf ccpxcon ;turn ccp module off movlw new_capt_ps ;load the w reg with ;the new prescaler ;move value and ccp on movwf ccpxcon ;load ccpxcon with this ;value
? 2012 microchip technology inc. preliminary ds41624b-page 239 pic16(l)f1512/3 21.1.5 capture during sleep capture mode depends upon the timer1 module for proper operation. there are two options for driving the timer1 module in capture mode. it can be driven by the instruction clock (f osc /4), or by an external clock source. when timer1 is clocked by f osc /4, timer1 will not increment during sleep. when the device wakes from sleep, timer1 will continue from its previous state. capture mode will operate during sleep when timer1 is clocked by an external clock source. 21.1.6 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 12.1 ?alternate pin function? for more information.
pic16(l)f1512/3 ds41624b-page 240 preliminary ? 2012 microchip technology inc. 21.2 compare mode the compare mode function described in this section is available and identical for al ccp modules. compare mode makes use of the 16-bit timer1 resource. the 16-bit value of the ccprxh:ccprxl register pair is constantly compared against the 16-bit value of the tmr1h:tmr1l register pair. when a match occurs, one of the following events can occur: ? toggle the ccpx output ? set the ccpx output ? clear the ccpx output ? generate a special event trigger ? generate a software interrupt the action on the pin is based on the value of the ccpxm<3:0> control bits of the ccpxcon register. at the same time, the interrupt flag ccpxif bit is set. all compare modes can generate an interrupt. figure 21-2 shows a simplified diagram of the compare operation. figure 21-2: compare mode operation block diagram 21.2.1 ccpx pin configuration the user must configure the ccpx pin as an output by clearing the associated tris bit. the ccp2 pin function can be moved to alternate pins using the apfcon register ( register 12-1 ). refer to section 12.1 ?alternate pin function? for more details. 21.2.2 timer1 mode resource in compare mode, timer1 must be running in either timer mode or synchronized counter mode. the compare operation may not work in asynchronous counter mode. see section 18.0 ?timer1 module with gate control? for more information on configuring timer1. 21.2.3 software interrupt mode when generate software interrupt mode is chosen (ccpxm<3:0> = 1010 ), the ccpx module does not assert control of the ccpx pin (see the ccpxcon register). 21.2.4 special event trigger when special event trigger mode is chosen (ccpxm<3:0> = 1011 ), the ccpx module does the following: ? resets timer1 ? starts an adc conversion if adc is enabled the ccpx module does not assert control of the ccpx pin in this mode. the special event trigger output of the ccp occurs immediately upon a match between the tmr1h, tmr1l register pair and the ccprxh, ccprxl register pair. the tmr1h, tmr1l register pair is not reset until the next rising edge of the timer1 clock. the special event trigger output starts an a/d conversion (if the a/d module is enabled). this allows the ccprxh, ccprxl register pair to effectively provide a 16-bit programmable period register for timer1. refer to section 16.2.5 ?special event trigger? for more information. note: clearing the ccpxcon register will force the ccpx compare output latch to the default low level. this is not the port i/o data latch. ccprxh ccprxl tmr1h tmr1l comparator qs r output logic special event trigger set ccpxif interrupt flag (pirx) match tris ccpxm<3:0> mode select output enable pin ccpx 4 note: clocking timer1 from the system clock (f osc ) should not be used in compare mode. in order for compare mode to recognize the trigger event on the ccpx pin, timer1 must be clocked from the instruction clock (f osc /4) or from an external clock source. note 1: the special event trigger from the ccpx module does not set interrupt flag bit tmr1if of the pir1 register. 2: removing the match condition by changing the contents of the ccprxh and ccprxl register pair, between the clock edge that generates the special event trigger and the clock edge that generates the timer1 reset, will preclude the reset from occurring.
? 2012 microchip technology inc. preliminary ds41624b-page 241 pic16(l)f1512/3 21.2.5 compare during sleep the compare mode is dependent upon the system clock (f osc ) for proper operation. since f osc is shut down during sleep mode, the compare mode will not function properly during sleep. 21.2.6 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 12.1 ?alternate pin function? for more information.
pic16(l)f1512/3 ds41624b-page 242 preliminary ? 2012 microchip technology inc. 21.3 pwm overview pulse-width modulation (pwm) is a scheme that provides power to a load by switching quickly between fully on and fully off states. the pwm signal resembles a square wave where the high portion of the signal is considered the on state and the low portion of the signal is considered the off state. the high portion, also known as the pulse width, can vary in time and is defined in steps. a larger number of steps applied, which lengthens the pulse width, also supplies more power to the load. lowering the number of steps applied, which shortens the pulse width, supplies less power. the pwm period is defined as the duration of one complete cycle or the total amount of on and off time combined. pwm resolution defines the maximum number of steps that can be present in a single pwm period. a higher resolution allows for more precise control of the pulse width time and in turn the power that is applied to the load. the term duty cycle describes the proportion of the on time to the off time and is expressed in percentages, where 0% is fully off and 100% is fully on. a lower duty cycle corresponds to less power applied and a higher duty cycle corresponds to more power applied. figure 21-3 shows a typical waveform of the pwm signal. 21.3.1 standard pwm operation the standard pwm function described in this section is available and identical for all ccp modules. the standard pwm mode generates a pulse-width modulation (pwm) signal on the ccpx pin with up to 10 bits of resolution. the period, duty cycle, and resolution are controlled by the following registers: ? pr2 registers ? t2con registers ? ccprxl registers ? ccpxcon registers figure 21-4 shows a simplified block diagram of pwm operation. figure 21-3: ccp pwm output signal figure 21-4: simplified pwm block diagram note 1: the corresponding tris bit must be cleared to enable the pwm output on the ccpx pin. 2: clearing the ccpxcon register will relinquish control of the ccpx pin. period pulse width tmr2 = 0 tmr2 = ccprxh:ccpxcon<5:4> tmr2 = pr2 ccprxl ccprxh (2) (slave) comparator tmr2 pr2 (1) rq s duty cycle registers ccpxcon<5:4> clear timer, toggle ccpx pin and latch duty cycle note 1: the 8-bit timer tmr2 register is concatenated with the 2-bit internal system clock (f osc ), or 2 bits of the prescaler, to create the 10-bit time base. 2: in pwm mode, ccprxh is a read-only register. tris ccpx comparator
? 2012 microchip technology inc. preliminary ds41624b-page 243 pic16(l)f1512/3 21.3.2 setup for pwm operation the following steps should be taken when configuring the ccp module for standard pwm operation: 1. disable the ccpx pin output driver by setting the associated tris bit. 2. load the pr2 register with the pwm period value. 3. configure the ccp module for the pwm mode by loading the ccpxcon register with the appropriate values. 4. load the ccprxl register and the dcxbx bits of the ccpxcon register, with the pwm duty cycle value. 5. configure and start timer2: ? clear the tmr2if interrupt flag bit of the pirx register. see note below. ? configure the t2ckps bits of the t2con register with the timer prescale value. ? enable the timer by setting the tmr2on bit of the t2con register. 6. enable pwm output pin: ? wait until the timer overflows and the tmr2if bit of the pir1 register is set. see note below. ? enable the ccpx pin output driver by clearing the associated tris bit. 21.3.3 timer2 timer resource the pwm standard mode makes use of the 8-bit timer2 timer resources to specify the pwm period. 21.3.4 pwm period the pwm period is specified by the pr2 register of timer2. the pwm period can be calculated using the formula of equation 21-1 . equation 21-1: pwm period when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ?tmr2 is cleared ? the ccpx pin is set. (exception: if the pwm duty cycle = 0%, the pin will not be set.) ? the pwm duty cycle is latched from ccprxl into ccprxh. 21.3.5 pwm duty cycle the pwm duty cycle is specified by writing a 10-bit value to multiple registers: ccprxl register and dcxb<1:0> bits of the ccpxcon register. the ccprxl contains the eight msbs and the dcxb<1:0> bits of the ccpxcon register contain the two lsbs. ccprxl and dcxb<1:0> bits of the ccpxcon register can be written to at any time. the duty cycle value is not latched into ccprxh until after the period completes (i.e., a match between pr2 and tmr2 registers occurs). while using the pwm, the ccprxh register is read-only. equation 21-2 is used to calculate the pwm pulse width. equation 21-3 is used to calculate the pwm duty cycle ratio. equation 21-2: pulse width equation 21-3: duty cycle ratio the ccprxh register and a 2-bit internal latch are used to double buffer the pwm duty cycle. this double buffering is essential for glitchless pwm operation. the 8-bit timer tmr2 register is concatenated with either the 2-bit internal system clock (f osc ), or two bits of the prescaler, to create the 10-bit time base. the system clock is used if the timer2 prescaler is set to 1:1. when the 10-bit time base matches the ccprxh and 2-bit latch, then the ccpx pin is cleared (see figure 21-4 ). note: in order to send a complete duty cycle and period on the first pwm output, the above steps must be included in the setup sequence. if it is not critical to start with a complete pwm signal on the first output, then step 6 may be ignored. pwm period pr 2 ?? 1 + ?? 4t osc ? ? ? = (tmr2 prescale value) note 1: t osc = 1/f osc note: the timer postscaler (see section 19.1 ?timer2 operation? ) is not used in the determination of the pwm frequency. pulse width ccprxl:ccpxcon<5:4> ?? ? = t osc ? (tmr2 prescale value) duty cycle ratio ccprxl:ccpxcon<5:4> ?? 4pr 2 1 + ?? ---------------------------------------------------------------------- - =
pic16(l)f1512/3 ds41624b-page 244 preliminary ? 2012 microchip technology inc. 21.3.6 pwm resolution the resolution determines the number of available duty cycles for a given period. for example, a 10-bit resolution will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. the maximum pwm resolution is 10 bits when pr2 is 255. the resolution is a function of the pr2 register value as shown by equation 21-4 . equation 21-4: pwm resolution table 21-1: example pwm frequencies and resolutions (f osc = 20 mhz) table 21-2: example pwm frequencies and resolutions (f osc = 8 mhz) note: if the pulse width value is greater than the period the assigned pwm pin(s) will remain unchanged. resolution 4pr 2 1 + ?? ?? log 2 ?? log ----------------------------------------- - bits = pwm frequency 1.22 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 pwm frequency 1.22 khz 4.90 khz 19.61 khz 76.92 khz 153.85 khz 200.0 khz timer prescale (1, 4, 16) 16 4 1 1 1 1 pr2 value 0x65 0x65 0x65 0x19 0x0c 0x09 maximum resolution (bits) 8 8 8 6 5 5
? 2012 microchip technology inc. preliminary ds41624b-page 245 pic16(l)f1512/3 21.3.7 operation in sleep mode in sleep mode, the tmr2 register will not increment and the state of the module will not change. if the ccpx pin is driving a value, it will continue to drive that value. when the device wakes up, tmr2 will continue from its previous state. 21.3.8 changes in system clock frequency the pwm frequency is derived from the system clock frequency. any changes in the system clock frequency will result in changes to the pwm frequency. see section 5.0 ?oscillator module (with fail-safe clock monitor)? for additional details. 21.3.9 effects of reset any reset will force all ports to input mode and the ccp registers to their reset states. 21.3.10 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 12.1 ?alternate pin function? for more information. table 21-3: summary of registers associated with standard pwm name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page apfcon ? ? ? ? ? ? sssel ccp2sel 106 ccp1con ? ? dc1b<1:0> ccp1m<3:0> 246 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pie2 osfie ? ? ? bclie ? ? ccp2ie 74 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 pir2 osfif ? ? ? bclif ? ?ccp2if 76 pr2 timer2 period register 179 * t2con ? t2outps<3:0> tmr2on t2ckps<1:0> 181 tmr2 timer2 module register 179 trisa trisa7 trisa6 trisa5 trisa4 trisa3 trisa2 trisa1 trisa0 108 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the pwm. * page provides register information.
pic16(l)f1512/3 ds41624b-page 246 preliminary ? 2012 microchip technology inc. 21.4 ccp control registers register 21-1: ccpxcon: ccpx control register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? dcxb<1:0> ccpxm<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other reset ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-4 dcxb<1:0>: pwm duty cycle least significant bits capture mode: unused compare mode: unused pwm mode: these bits are the two lsbs of the pwm duty cycle. the eight msbs are found in ccprxl. bit 3-0 ccpxm<3:0>: ccpx mode select bits 0000 = capture/compare/pwm off (resets ccpx module) 0001 = reserved 0010 = compare mode: toggle output on match 0011 = reserved 0100 = capture mode: every falling edge 0101 = capture mode: every rising edge 0110 = capture mode: every 4th rising edge 0111 = capture mode: every 16th rising edge 1000 = compare mode: set output on compare match (set ccpxif) 1001 = compare mode: clear output on compare match (set ccpxif) 1010 = compare mode: generate software interrupt only 1011 = compare mode: special event trigger (sets ccpxif bit, starts a/d conversion if a/d module is enabled) 11xx =pwm mode
? 2012 microchip technology inc. preliminary ds41624b-page 247 pic16(l)f1512/3 22.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) the enhanced universal synchronous asynchronous receiver transmitter (eusart) module is a serial i/o communications peripheral. it contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. the eusart, also known as a serial communications interface (sci), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. full-duplex mode is useful for communications with peripheral systems, such as crt terminals and personal computers. half-duplex synchronous mode is intended for communications with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms or other microcontrollers. these devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. the eusart module includes the following capabilities: ? full-duplex asynchronous transmit and receive ? two-character input buffer ? one-character output buffer ? programmable 8-bit or 9-bit character length ? address detection in 9-bit mode ? input buffer overrun error detection ? received character framing error detection ? half-duplex synchronous master ? half-duplex synchronous slave ? programmable clock polarity in synchronous modes ? sleep operation the eusart module implements the following additional features, making it ideally suited for use in local interconnect network (lin) bus systems: ? automatic detection and calibration of the baud rate ? wake-up on break reception ? 13-bit break character transmit block diagrams of the eusart transmitter and receiver are shown in figure 22-1 and figure 22-2 . figure 22-1: eusart transmi t block diagram txif txie interrupt txen tx9d msb lsb data bus txreg register transmit shift register (tsr) (8) 0 tx9 trmt spen tx/ck pin pin buffer and control 8 spbrgl spbrgh brg16 f osc n n + 1 multiplier x4 x16 x64 sync 1x00 0 brgh x110 0 brg16 x101 0 baud rate generator ???
pic16(l)f1512/3 ds41624b-page 248 preliminary ? 2012 microchip technology inc. figure 22-2: eusart receiv e block diagram the operation of the eusart module is controlled through three registers: ? transmit status and control (txsta) ? receive status and control (rcsta) ? baud rate control (baudcon) these registers are detailed in register 22-1 , register 22-2 and register 22-3 , respectively. when the receiver or transmitter section is not enabled then the corresponding rx or tx pin may be used for general purpose input and output. rx/dt pin pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 stop start (8) 7 1 0 rx9 ? ? ? spbrgl spbrgh brg16 rcidl f osc n n + 1 multiplier x4 x16 x64 sync 1x00 0 brgh x110 0 brg16 x101 0 baud rate generator
? 2012 microchip technology inc. preliminary ds41624b-page 249 pic16(l)f1512/3 22.1 eusart asynchronous mode the eusart transmits and receives data using the standard non-return-to-zero (nrz) format. nrz is implemented with two levels: a v oh mark state which represents a ? 1 ? data bit, and a v ol space state which represents a ? 0 ? data bit. nrz refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. an nrz transmission port idles in the mark state. each character transmission consists of one start bit followed by eight or nine data bits and is always terminated by one or more stop bits. the start bit is always a space and the stop bits are always marks. the most common data format is eight bits. each transmitted bit persists for a period of 1/(baud rate). an on-chip dedicated 8-bit/16-bit baud rate generator is used to derive standard baud rate frequencies from the system oscillator. see tab l e 2 2- 5 for examples of baud rate configurations. the eusart transmits and receives the lsb first. the eusart?s transmitter and receiver are functionally independent, but share the same data format and baud rate. parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 22.1.1 eusart asynchronous transmitter the eusart transmitter block diagram is shown in figure 22-1 . the heart of the transmitter is the serial transmit shift register (tsr), which is not directly accessible by software. the tsr obtains its data from the transmit buffer, which is the txreg register. 22.1.1.1 enabling the transmitter the eusart transmitter is enabled for asynchronous operations by configuring the following three control bits: ?txen = 1 ? sync = 0 ? spen = 1 all other eusart control bits are assumed to be in their default state. setting the txen bit of the txsta register enables the transmitter circuitry of the eusart. clearing the sync bit of the txsta register configures the eusart for asynchronous operation. setting the spen bit of the rcsta register enables the eusart and automatically configures the tx/ck i/o pin as an output. if the tx/ck pin is shared with an analog peripheral, the analog i/o function must be disabled by clearing the corresponding ansel bit. 22.1.1.2 transmitting data a transmission is initiated by writing a character to the txreg register. if this is the first character, or the previous character has been completely flushed from the tsr, the data in the txreg is immediately transferred to the tsr register. if the tsr still contains all or part of a previous character, the new character data is held in the txreg until the stop bit of the previous character has been transmitted. the pending character in the txreg is then transferred to the tsr in one t cy immediately following the stop bit transmission. the transmission of the start bit, data bits and stop bit sequence commences immediately following the transfer of the data to the tsr from the txreg. 22.1.1.3 transmit data polarity the polarity of the transmit data can be controlled with the sckp bit of the baudcon register. the default state of this bit is ? 0 ? which selects high true transmit idle and data bits. setting the sckp bit to ? 1 ? will invert the transmit data resulting in low true idle and data bits. the sckp bit controls transmit data polarity in asynchronous mode only. in synchronous mode, the sckp bit has a different function. see section 22.5.1.2 ?clock polarity? . 22.1.1.4 transmit interrupt flag the txif interrupt flag bit of the pir1 register is set whenever the eusart transmitter is enabled and no character is being held for transmission in the txreg. in other words, the txif bit is only clear when the tsr is busy with a character and a new character has been queued for transmission in the txreg. the txif flag bit is not cleared immediately upon writing txreg. txif becomes valid in the second instruction cycle following the write execution. polling txif immediately following the txreg write will return invalid results. the txif bit is read-only, it cannot be set or cleared by software. the txif interrupt can be enabled by setting the txie interrupt enable bit of the pie1 register. however, the txif flag bit will be set whenever the txreg is empty, regardless of the state of txie enable bit. to use interrupts when transmitting data, set the txie bit only when there is more data to send. clear the txie interrupt enable bit upon writing the last character of the transmission to the txreg. note 1: the txif transmitter interrupt flag is set when the txen enable bit is set.
pic16(l)f1512/3 ds41624b-page 250 preliminary ? 2012 microchip technology inc. 22.1.1.5 tsr status the trmt bit of the txsta register indicates the status of the tsr register. this is a read-only bit. the trmt bit is set when the tsr register is empty and is cleared when a character is transferred to the tsr register from the txreg. the trmt bit remains clear until all bits have been shifted out of the tsr register. no interrupt logic is tied to this bit, so the user has to poll this bit to determine the tsr status. 22.1.1.6 transmitting 9-bit characters the eusart supports 9-bit character transmissions. when the tx9 bit of the txsta register is set, the eusart will shift nine bits out for each character transmitted. the tx9d bit of the txsta register is the ninth, and most significant, data bit. when transmitting 9-bit data, the tx9d data bit must be written before writing the eight least significant bits into the txreg. all nine bits of data will be transferred to the tsr shift register immediately after the txreg is written. a special 9-bit address mode is available for use with multiple receivers. see section 22.1.2.7 ?address detection? for more information on the address mode. 22.1.1.7 asynchronous transmission set-up: 1. initialize the spbrgh, spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 22.4 ?eusart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if 9-bit transmission is desired, set the tx9 control bit. a set ninth data bit will indicate that the eight least significant data bits are an address when the receiver is set for address detection. 4. set sckp bit if inverted transmit is desired. 5. enable the transmission by setting the txen control bit. this will cause the txif interrupt bit to be set. 6. if interrupts are desired, set the txie interrupt enable bit of the pie1 register. an interrupt will occur immediately provided that the gie and peie bits of the intcon register are also set. 7. if 9-bit transmission is selected, the ninth bit should be loaded into the tx9d data bit. 8. load 8-bit data into the txreg register. this will start the transmission. figure 22-3: asynchronous transmission note: the tsr register is not mapped in data memory, so it is not available to the user. word 1 stop bit word 1 transmit shift reg. start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) tx/ck txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy pin
? 2012 microchip technology inc. preliminary ds41624b-page 251 pic16(l)f1512/3 figure 22-4: asynchronous transmiss ion (back-to-back) table 22-1: summary of registers asso ciated with asynchronous transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ? wue abden 258 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 rcsta spen rx9 sren cren adden ferr oerr rx9d 257 spbrgl brg<7:0> 259 * spbrgh brg<15:8> 259 * trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 115 txreg eusart transmit data register 249 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 256 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for asynchronous transmission. * page provides register information. transmit shift reg. write to txreg brg output (shift clock) tx/ck trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy pin txif bit (transmit buffer reg. empty flag)
pic16(l)f1512/3 ds41624b-page 252 preliminary ? 2012 microchip technology inc. 22.1.2 eusart asynchronous receiver the asynchronous mode is typically used in rs-232 systems. the receiver block diagram is shown in figure 22-2 . the data is received on the rx/dt pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial receive shift register (rsr) operates at the bit rate. when all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character first-in-first-out (fifo) memory. the fifo buffering allows reception of two complete characters and the start of a third character before software must start servicing the eusart receiver. the fifo and rsr registers are not directly accessible by software. access to the received data is via the rcreg register. 22.1.2.1 enabling the receiver the eusart receiver is enabled for asynchronous operation by configuring the following three control bits: ? cren = 1 ? sync = 0 ? spen = 1 all other eusart control bits are assumed to be in their default state. setting the cren bit of the rcsta register enables the receiver circuitry of the eusart. clearing the sync bit of the txsta register configures the eusart for asynchronous operation. setting the spen bit of the rcsta register enables the eusart. the programmer must set the corresponding tris bit to configure the rx/dt i/o pin as an input. 22.1.2.2 receiving data the receiver data recovery circuit initiates character reception on the falling edge of the first bit. the first bit, also known as the start bit, is always a zero. the data recovery circuit counts one-half bit time to the center of the start bit and verifies that the bit is still a zero. if it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the start bit. if the start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. the bit is then sampled by a majority detect circuit and the resulting ? 0 ? or ? 1 ? is shifted into the rsr. this repeats until all data bits have been sampled and shifted into the rsr. one final bit time is measured and the level sampled. this is the stop bit, which is always a ? 1 ?. if the data recovery circuit samples a ? 0 ? in the stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. see section 22.1.2.4 ?receive framing error? for more information on framing errors. immediately after all data bits and the stop bit have been received, the character in the rsr is transferred to the eusart receive fifo and the rcif interrupt flag bit of the pir1 register is set. the top character in the fifo is transferred out of the fifo by reading the rcreg register. 22.1.2.3 receive interrupts the rcif interrupt flag bit of the pir1 register is set whenever the eusart receiver is enabled and there is an unread character in the receive fifo. the rcif interrupt flag bit is read-only, it cannot be set or cleared by software. rcif interrupts are enabled by setting all of the following bits: ? rcie, interrupt enable bit of the pie1 register ? peie, peripheral interrupt enable bit of the intcon register ? gie, global interrupt enable bit of the intcon register the rcif interrupt flag bit will be set when there is an unread character in the fifo, regardless of the state of interrupt enable bits. note 1: if the rx/dt function is on an analog pin, the corresponding ansel bit must be cleared for the receiver to function. note: if the receive fifo is overrun, no additional characters will be received until the overrun condition is cleared. see section 22.1.2.5 ?receive overrun error? for more information on overrun errors.
? 2012 microchip technology inc. preliminary ds41624b-page 253 pic16(l)f1512/3 22.1.2.4 receive framing error each character in the receive fifo buffer has a corresponding framing error status bit. a framing error indicates that a stop bit was not seen at the expected time. the framing error status is accessed via the ferr bit of the rcsta register. the ferr bit represents the status of the top unread character in the receive fifo. therefore, the ferr bit must be read before reading the rcreg. the ferr bit is read-only and only applies to the top unread character in the receive fifo. a framing error (ferr = 1 ) does not preclude reception of additional characters. it is not necessary to clear the ferr bit. reading the next character from the fifo buffer will advance the fifo to the next character and the next corresponding framing error. the ferr bit can be forced clear by clearing the spen bit of the rcsta register which resets the eusart. clearing the cren bit of the rcsta register does not affect the ferr bit. a framing error by itself does not generate an interrupt. 22.1.2.5 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before the fifo is accessed. when this happens the oerr bit of the rcsta register is set. the characters already in the fifo buffer can be read but no additional characters will be received until the error is cleared. the error must be cleared by either clearing the cren bit of the rcsta register or by resetting the eusart by clearing the spen bit of the rcsta register. 22.1.2.6 receiving 9-bit characters the eusart supports 9-bit character reception. when the rx9 bit of the rcsta register is set the eusart will shift nine bits into the rsr for each character received. the rx9d bit of the rcsta register is the ninth and most significant data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the eight least significant bits from the rcreg. 22.1.2.7 address detection a special address detection mode is available for use when multiple receivers share the same transmission line, such as in rs-485 systems. address detection is enabled by setting the adden bit of the rcsta register. address detection requires 9-bit character reception. when address detection is enabled, only characters with the ninth data bit set will be transferred to the receive fifo buffer, thereby setting the rcif interrupt bit. all other characters will be ignored. upon receiving an address character, user software determines if the address matches its own. upon address match, user software must disable address detection by clearing the adden bit before the next stop bit occurs. when user software detects the end of the message, determined by the message protocol used, software places the receiver back into the address detection mode by setting the adden bit. note: if all receive characters in the receive fifo have framing errors, repeated reads of the rcreg will not clear the ferr bit.
pic16(l)f1512/3 ds41624b-page 254 preliminary ? 2012 microchip technology inc. 22.1.2.8 asynchronous reception set-up: 1. initialize the spbrgh, spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 22.4 ?eusart baud rate generator (brg)? ). 2. clear the ansel bit for the rx pin (if applicable). 3. enable the serial port by setting the spen bit. the sync bit must be clear for asynchronous operation. 4. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 5. if 9-bit reception is desired, set the rx9 bit. 6. enable reception by setting the cren bit. 7. the rcif interrupt flag bit will be set when a character is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcie interrupt enable bit was also set. 8. read the rcsta register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. get the received eight least significant data bits from the receive buffer by reading the rcreg register. 10. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 22.1.2.9 9-bit address detection mode set-up this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrgh, spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 22.4 ?eusart baud rate generator (brg)? ). 2. clear the ansel bit for the rx pin (if applicable). 3. enable the serial port by setting the spen bit. the sync bit must be clear for asynchronous operation. 4. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 5. enable 9-bit reception by setting the rx9 bit. 6. enable address detection by setting the adden bit. 7. enable reception by setting the cren bit. 8. the rcif interrupt flag bit will be set when a character with the ninth bit set is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcie interrupt enable bit was also set. 9. read the rcsta register to get the error flags. the ninth data bit will always be set. 10. get the received eight least significant data bits from the receive buffer by reading the rcreg register. software determines if this is the device?s address. 11. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 12. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and generate interrupts. figure 22-5: asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx/dt pin reg rcv buffer reg. rcv shift read rcv buffer reg. rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx in put. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. rcidl
? 2012 microchip technology inc. preliminary ds41624b-page 255 pic16(l)f1512/3 table 22-2: summary of registers asso ciated with asynchronous reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ?wue abden 258 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 rcreg eusart receive data register 252 * rcsta spen rx9 sren cren adden ferr oerr rx9d 257 spbrgl brg<7:0> 259 * spbrgh brg<15:8> 259 * trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 115 txsta csrc tx9 txen sync sendb brgh trmt tx9d 256 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for asynchronous reception. * page provides register information.
pic16(l)f1512/3 ds41624b-page 256 preliminary ? 2012 microchip technology inc. 22.2 clock accuracy with asynchronous operation the factory calibrates the internal oscillator block output (intosc). however, the intosc frequency may drift as v dd or temperature changes, and this directly affects the asynchronous baud rate. two methods may be used to adjust the baud rate clock, but both require a reference clock source of some kind. the first (preferred) method uses the osctune register to adjust the intosc output. adjusting the value in the osctune register allows for fine resolution changes to the system clock source. see section 5.2.2 ?internal clock sources? for more information. the other method adjusts the value in the baud rate generator. this can be done automatically with the auto-baud detect feature (see section 22.4.1 ?auto-baud detect? ). there may not be fine enough resolution when adjusting the baud rate generator to compensate for a gradual change in the peripheral clock frequency. 22.3 eusart control registers register 22-1: txsta: transmit status and control register r/w-/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-1/1 r/w-0/0 csrc tx9 txen (1) sync sendb brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 csrc: clock source select bit asynchronous mode : don?t care synchronous mode : 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled bit 4 sync: eusart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 sendb: send break character bit asynchronous mode : 1 = send sync break on next transmission (cleared by hardware upon completion) 0 = sync break transmission completed synchronous mode : don?t care bit 2 brgh: high baud rate select bit asynchronous mode : 1 = high speed 0 = low speed synchronous mode: unused in this mode bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: ninth bit of transmit data can be address/data bit or a parity bit. note 1: sren/cren overrides txen in sync mode.
? 2012 microchip technology inc. preliminary ds41624b-page 257 pic16(l)f1512/3 register 22-2: rcsta: receive status and control register (1) r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-0/0 r-0/0 r-x/x spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : don?t care synchronous mode ? master : 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave don?t care bit 4 cren: continuous receive enable bit asynchronous mode : 1 = enables receiver 0 = disables receiver synchronous mode : 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enables address detection, enable interrupt and load the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 8-bit (rx9 = 0 ) : don?t care bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: ninth bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware.
pic16(l)f1512/3 ds41624b-page 258 preliminary ? 2012 microchip technology inc. register 22-3: baudcon: ba ud rate control register r-0/0 r-1/1 u-0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 abdovf rcidl ? sckp brg16 ? wue abden bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 abdovf: auto-baud detect overflow bit asynchronous mode : 1 = auto-baud timer overflowed 0 = auto-baud timer did not overflow synchronous mode : don?t care bit 6 rcidl : receive idle flag bit asynchronous mode : 1 = receiver is idle 0 = start bit has been received and the receiver is receiving synchronous mode : don?t care bit 5 unimplemented: read as ? 0 ? bit 4 sckp : synchronous clock polarity select bit asynchronous mode : 1 = transmit inverted data to the tx/ck pin 0 = transmit non-inverted data to the tx/ck pin synchronous mode : 1 = data is clocked on rising edge of the clock 0 = data is clocked on falling edge of the clock bit 3 brg16: 16-bit baud rate generator bit 1 = 16-bit baud rate generator is used 0 = 8-bit baud rate generator is used bit 2 unimplemented: read as ? 0 ? bit 1 wue: wake-up enable bit asynchronous mode : 1 = receiver is waiting for a falling edge. no character will be received, byte rcif will be set. wue will automatically clear after rcif is set. 0 = receiver is operating normally synchronous mode : don?t care bit 0 abden : auto-baud detect enable bit asynchronous mode : 1 = auto-baud detect mode is enabled (clears when auto-baud is complete) 0 = auto-baud detect mode is disabled synchronous mode : don?t care
? 2012 microchip technology inc. preliminary ds41624b-page 259 pic16(l)f1512/3 22.4 eusart baud rate generator (brg) the baud rate generator (brg) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous eusart operation. by default, the brg operates in 8-bit mode. setting the brg16 bit of the baudcon register selects 16-bit mode. the spbrgh, spbrgl register pair determines the period of the free running baud rate timer. in asynchronous mode the multiplier of the baud rate period is determined by both the brgh bit of the txsta register and the brg16 bit of the baudcon register. in synchronous mode, the brgh bit is ignored. table 22-3 contains the formulas for determining the baud rate. example 22-1 provides a sample calculation for determining the baud rate and baud rate error. typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in table 22-3 . it may be advantageous to use the high baud rate (brgh = 1 ), or the 16-bit brg (brg16 = 1 ) to reduce the baud rate error. the 16-bit brg mode is used to achieve slow baud rates for fast oscillator frequencies. writing a new value to the spbrgh, spbrgl register pair causes the brg timer to be reset (or cleared). this ensures that the brg does not wait for a timer overflow before outputting the new baud rate. if the system clock is changed during an active receive operation, a receive error or data loss may result. to avoid this problem, check the status of the rcidl bit to make sure that the receive operation is idle before changing the system clock. example 22-1: calculating baud rate error for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, 8-bit brg: solving for spbrgh:spbrgl: x f osc desired baud rate --------------------------------------------- 64 --------------------------------------------- 1 ? = desired baud rate f osc 64 [spbrgh:spbrgl] 1 + ?? ----------------------------------------------------------------------- - = 16000000 9600 ----------------------- - 64 ----------------------- -1 ? = 25.042 ?? 25 == calculated baud rate 16000000 64 25 1 + ?? -------------------------- - = 9615 = error calc. baud rate desired baud rate ? desired baud rate -------------------------------------------------------------------------------------------- = 9615 9600 ? ?? 9600 ---------------------------------- 0 . 1 6 % ==
pic16(l)f1512/3 ds41624b-page 260 preliminary ? 2012 microchip technology inc. table 22-3: baud rate formulas table 22-4: summary of registers as sociated with the baud rate generator configuration bits brg/eusart mode baud rate formula sync brg16 brgh 000 8-bit/asynchronous f osc /[64 (n+1)] 001 8-bit/asynchronous f osc /[16 (n+1)] 010 16-bit/asynchronous 011 16-bit/asynchronous f osc /[4 (n+1)] 10x 8-bit/synchronous 11x 16-bit/synchronous legend: x = don?t care, n = value of spbrgh, spbrgl register pair. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ? wue abden 258 rcsta spen rx9 sren cren adden ferr oerr rx9d 257 spbrgl brg<7:0> 259 * spbrgh brg<15:8> 259 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 256 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for the baud rate generator. * page provides register information.
? 2012 microchip technology inc. preliminary ds41624b-page 261 pic16(l)f1512/3 table 22-5: baud rates for asynchronous modes baud rate sync = 0 , brgh = 0 , brg16 = 0 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300?? ? ?? ? ?? ? ?? ? 1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 2404 0.16 129 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 29 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k ? ? ? 57.60k 0.00 7? ? ? 57.60k 0.00 2 115.2k ? ? ? ? ? ? ? ? ? ? ? ? baud rate sync = 0 , brgh = 0 , brg16 = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ? ? ? 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 ? ? ? 9600 9615 0.16 12 ? ? ? 9600 0.00 5 ? ? ? 10417 10417 0.00 11 10417 0.00 5 ? ? ? ? ? ? 19.2k ? ? ? ? ? ? 19.20k 0.00 2 ? ? ? 57.6k ? ? ? ? ? ? 57.60k 0.00 0 ? ? ? 115.2k ? ? ? ? ? ? ? ? ? ? ? ? baud rate sync = 0 , brgh = 1 , brg16 = 0 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ?? ? ?? ? ?? ? ?? ? 1200 ? ? ? ? ? ? ? ? ? ? ? ? 2400 ? ? ? ? ? ? ? ? ? ?? ? 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.82k -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.64k -1.36 10 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5
pic16(l)f1512/3 ds41624b-page 262 preliminary ? 2012 microchip technology inc. baud rate sync = 0 , brgh = 1 , brg16 = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ?? ? ? ? ? ? ? ? 300 0.16 207 1200 ? ? ? 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 ? ? ? 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 ? ? ? 57.6k 55556 -3.55 8 ? ? ? 57.60k 0.00 3 ? ? ? 115.2k ? ? ? ? ? ? 115.2k 0.00 1 ? ? ? baud rate sync = 0 , brgh = 0 , brg16 = 1 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 -0.01 4166 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303 1200 1200 -0.03 1041 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2399 -0.03 520 2400 0.00 479 2398 -0.08 416 2400 0.00 287 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.818 -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.636 -1.36 10 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5 baud rate sync = 0 , brgh = 0 , brg16 = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 ? ? ? 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 ? ? ? 57.6k 55556 -3.55 8 ? ? ? 57.60k 0.00 3 ? ? ? 115.2k ? ? ? ? ? ? 115.2k 0.00 1 ? ? ? table 22-5: baud rates for asynchronous modes (continued)
? 2012 microchip technology inc. preliminary ds41624b-page 263 pic16(l)f1512/3 baud rate sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215 1200 1200 -0.01 4166 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303 2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9597 -0.03 520 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 479 10425 0.08 441 10417 0.00 383 10433 0.16 264 19.2k 19.23k 0.16 259 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143 57.6k 57.47k -0.22 86 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 116.3k 0.94 42 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 baud rate sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 ? ? ? 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 ? ? ? table 22-5: baud rates for asynchronous modes (continued)
pic16(l)f1512/3 ds41624b-page 264 preliminary ? 2012 microchip technology inc. 22.4.1 a uto-baud detect the eusart module supports automatic detection and calibration of the baud rate. in the auto-baud detect (abd) mode, the clock to the brg is reversed. rather than the brg clocking the incoming rx signal, the rx signal is timing the brg. the baud rate generator is used to time the period of a received 55h (ascii ?u?) which is the sync character for the lin bus. the unique feature of this character is that it has five rising edges including the stop bit edge. setting the abden bit of the baudcon register starts the auto-baud calibration sequence ( figure 22-6 ). while the abd sequence takes place, the eusart state machine is held in idle. on the first rising edge of the receive line, after the start bit, the spbrg begins counting up using the brg counter clock as shown in table 22-6 . the fifth rising edge will occur on the rx pin at the end of the eighth bit period. at that time, an accumulated value totaling the proper brg period is left in the spbrgh, spbrgl register pair, the abden bit is automatically cleared and the rcif interrupt flag is set. the value in the rcreg needs to be read to clear the rcif interrupt. rcreg content should be discarded. when calibrating for modes that do not use the spbrgh register the user can verify that the spbrgl register did not overflow by checking for 00h in the spbrgh register. the brg auto-baud clock is determined by the brg16 and brgh bits as shown in table 22-6 . during abd, both the spbrgh and spbrgl registers are used as a 16-bit counter, independent of the brg16 bit setting. while calibrating the baud rate period, the spbrgh and spbrgl registers are clocked at 1/8th the brg base clock rate. the resulting byte measurement is the average bit time when clocked at full speed. table 22-6: brg counter clock rates figure 22-6: automatic baud rate calibration note 1: if the wue bit is set with the abden bit, auto-baud detection will occur on the byte following the break character (see section 22.4.3 ?auto-wake-up on break? ). 2: it is up to the user to determine that the incoming character baud rate is within the range of the selected brg clock source. some combinations of oscillator frequency and eusart baud rates are not possible. 3: during the auto-baud process, the auto-baud counter starts counting at 1. upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the spbrgh:spbrgl register pair. brg16 brgh brg base clock brg abd clock 00 f osc /64 f osc /512 01 f osc /16 f osc /128 10 f osc /16 f osc /128 11 f osc /4 f osc /32 note: during the abd sequence, spbrgl and spbrgh registers are both used as a 16-bit counter, independent of brg16 setting. brg value rx pin abden bit rcif bit bit 0 bit 1 (interrupt) read rcreg brg clock start auto cleared set by user xxxxh 0000h edge #1 bit 2 bit 3 edge #2 bit 4 bit 5 edge #3 bit 6 bit 7 edge #4 stop bit edge #5 001ch note 1: the abd sequence requires the eusart module to be configured in asynchronous mode. spbrgl xxh 1ch spbrgh xxh 00h rcidl
? 2012 microchip technology inc. preliminary ds41624b-page 265 pic16(l)f1512/3 22.4.2 auto-baud overflow during the course of automatic baud detection, the abdovf bit of the baudcon register will be set if the baud rate counter overflows before the fifth rising edge is detected on the rx pin. the abdovf bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the spbrgh:spbrgl register pair. after the abdovf bit has been set, the counter continues to count until the fifth rising edge is detected on the rx pin. upon detecting the fifth rx edge, the hardware will set the rcif interrupt flag and clear the abden bit of the baudcon register. the rcif flag can be subsequently cleared by reading the rcreg register. the abdovf flag of the baudcon register can be cleared by software directly. to terminate the auto-baud process before the rcif flag is set, clear the abden bit then clear the abdovf bit of the baudcon register. the abdovf bit will remain set if the abden bit is not cleared first. 22.4.3 auto-wake-up on break during sleep mode, all clocks to the eusart are suspended. because of this, the baud rate generator is inactive and a proper character reception cannot be performed. the auto-wake-up feature allows the controller to wake-up due to activity on the rx/dt line. this feature is available only in asynchronous mode. the auto-wake-up feature is enabled by setting the wue bit of the baudcon register. once set, the normal receive sequence on rx/dt is disabled, and the eusart remains in an idle state, monitoring for a wake-up event independent of the cpu mode. a wake-up event consists of a high-to-low transition on the rx/dt line. (this coincides with the start of a sync break or a wake-up signal character for the lin protocol.) the eusart module generates an rcif interrupt coincident with the wake-up event. the interrupt is generated synchronously to the q clocks in normal cpu operating modes ( figure 22-7 ), and asynchronously if the device is in sleep mode ( figure 22-8 ). the interrupt condition is cleared by reading the rcreg register. the wue bit is automatically cleared by the low-to-high transition on the rx line at the end of the break. this signals to the user that the break event is over. at this point, the eusart module is in idle mode waiting to receive the next character. 22.4.3.1 special considerations break character to avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. when the wake-up is enabled the function works independent of the low time on the data stream. if the wue bit is set and a valid non-zero character is received, the low time from the start bit to the first rising edge will be interpreted as the wake-up event. the remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. therefore, the initial character in the transmission must be all ? 0 ?s. this must be 10 or more bit times, 13-bit times recommended for lin bus, or any number of bit times for standard rs-232 devices. oscillator start-up time oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., lp, xt or hs mode). the sync break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the eusart. wue bit the wake-up event causes a receive interrupt by setting the rcif bit. the wue bit is cleared in hardware by a rising edge on rx/dt. the interrupt condition is then cleared in software by reading the rcreg register and discarding its contents. to ensure that no actual data is lost, check the rcidl bit to verify that a receive operation is not in process before setting the wue bit. if a receive operation is not occurring, the wue bit may then be set just prior to entering the sleep mode.
pic16(l)f1512/3 ds41624b-page 266 preliminary ? 2012 microchip technology inc. figure 22-7: auto-wake-up bit (wue) timing during normal operation figure 22-8: auto-wake-up bit (wue) timings during sleep q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx/dt line rcif bit set by user auto cleared cleared due to user read of rcreg note 1: the eusart remains in idle while the wue bit is set. q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx/dt line rcif bit set by user auto cleared cleared due to user read of rcreg sleep command executed note 1 note 1: if the wake-up event requires long oscillator warm-up time, the automatic clearing of the wue bit can occur while the stposc signal is still active. this sequence should not depend on the presence of q clocks. 2: the eusart remains in idle while the wue bit is set. sleep ends
? 2012 microchip technology inc. preliminary ds41624b-page 267 pic16(l)f1512/3 22.4.4 break character sequence the eusart module has the capability of sending the special break character sequences that are required by the lin bus standard. a break character consists of a start bit, followed by 12 ? 0 ? bits and a stop bit. to send a break character, set the sendb and txen bits of the txsta register. the break character transmission is then initiated by a write to the txreg. the value of data written to txreg will be ignored and all ? 0 ?s will be transmitted. the sendb bit is automatically reset by hardware after the corresponding stop bit is sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync character in the lin specification). the trmt bit of the txsta register indicates when the transmit operation is active or idle, just as it does during normal transmission. see figure 22-9 for the timing of the break character sequence. 22.4.4.1 break and sync transmit sequence the following sequence will start a message frame header made up of a break, followed by an auto-baud sync byte. this sequence is typical of a lin bus master. 1. configure the eusart for the desired mode. 2. set the txen and sendb bits to enable the break sequence. 3. load the txreg with a dummy character to initiate transmission (the value is ignored). 4. write ?55h? to txreg to load the sync character into the transmit fifo buffer. 5. after the break has been sent, the sendb bit is reset by hardware and the sync character is then transmitted. when the txreg becomes empty, as indicated by the txif, the next data byte can be written to txreg. 22.4.5 receiving a break character the enhanced eusart module can receive a break character in two ways. the first method to detect a break character uses the ferr bit of the rcsta register and the received data as indicated by rcreg. the baud rate generator is assumed to have been initialized to the expected baud rate. a break character has been received when; ? rcif bit is set ? ferr bit is set ? rcreg = 00h the second method uses the auto-wake-up feature described in section 22.4.3 ?auto-wake-up on break? . by enabling this feature, the eusart will sample the next two transitions on rx/dt, cause an rcif interrupt, and receive the next data byte followed by another interrupt. note that following a break character, the user will typically want to enable the auto-baud detect feature. for both methods, the user can set the abden bit of the baudcon register before placing the eusart in sleep mode. figure 22-9: send break character sequence write to txreg dummy write brg output (shift clock) start bit bit 0 bit 1 bit 11 stop bit break txif bit (transmit interrupt flag) tx (pin) trmt bit (transmit shift empty flag) sendb (send break control bit) sendb sampled here auto cleared
pic16(l)f1512/3 ds41624b-page 268 preliminary ? 2012 microchip technology inc. 22.5 eusart synchronous mode synchronous serial communications are typically used in systems with a single master and one or more slaves. the master device contains the necessary circuitry for baud rate generation and supplies the clock for all devices in the system. slave devices can take advantage of the master clock by eliminating the internal clock generation circuitry. there are two signal lines in synchronous mode: a bidirectional data line and a clock line. slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and trans- mit shift registers. since the data line is bidirectional, synchronous operation is half-duplex only. half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. the eusart can operate as either a master or slave device. start and stop bits are not used in synchronous transmissions. 22.5.1 synchronous master mode the following bits are used to configure the eusart for synchronous master operation: ? sync = 1 ? csrc = 1 ? sren = 0 (for transmit); sren = 1 (for receive) ? cren = 0 (for transmit); cren = 1 (for receive) ? spen = 1 setting the sync bit of the txsta register configures the device for synchronous operation. setting the csrc bit of the txsta register configures the device as a master. clearing the sren and cren bits of the rcsta register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rcsta register enables the eusart. 22.5.1.1 master clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device config- ured as a master transmits the clock on the tx/ck line. the tx/ck pin output driver is automatically enabled when the eusart is configured for synchronous transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. one clock cycle is generated for each data bit. only as many clock cycles are generated as there are data bits. 22.5.1.2 clock polarity a clock polarity option is provided for microwire compatibility. clock polarity is selected with the sckp bit of the baudcon register. setting the sckp bit sets the clock idle state as high. when the sckp bit is set, the data changes on the falling edge of each clock. clearing the sckp bit sets the idle state as low. when the sckp bit is cleared, the data changes on the rising edge of each clock. 22.5.1.3 synchronous master transmission data is transferred out of the device on the rx/dt pin. the rx/dt and tx/ck pin output drivers are automat- ically enabled when the eusart is configured for synchronous master transmit operation. a transmission is initiated by writing a character to the txreg register. if the tsr still contains all or part of a previous character the new character data is held in the txreg until the last bit of the previous character has been transmitted. if this is the first character, or the previous character has been completely flushed from the tsr, the data in the txreg is immediately transferred to the tsr. the transmission of the character commences immediately following the transfer of the data to the tsr from the txreg. each data bit changes on the leading edge of the master clock and remains valid until the subsequent leading clock edge. 22.5.1.4 synchronous master transmission set-up: 1. initialize the spbrgh, spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 22.4 ?eusart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. disable receive mode by clearing bits sren and cren. 4. enable transmit mode by setting the txen bit. 5. if 9-bit transmission is desired, set the tx9 bit. 6. if interrupts are desired, set the txie bit of the pie1 register and the gie and peie bits of the intcon register. 7. if 9-bit transmission is selected, the ninth bit should be loaded in the tx9d bit. 8. start transmission by loading data to the txreg register. note: the tsr register is not mapped in data memory, so it is not available to the user.
? 2012 microchip technology inc. preliminary ds41624b-page 269 pic16(l)f1512/3 figure 22-10: synchronous transmission figure 22-11: synchronous transmis sion (through txen) table 22-7: summary of registers as sociated with synchronous master transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ? wue abden 258 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 rcsta spen rx9 sren cren adden ferr oerr rx9d 257 spbrgl brg<7:0> 259 * spbrgh brg<15:8> 259 * trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 115 txreg eusart transmit data register 249 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 256 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master transmission. * page provides register information. bit 0 bit 1 bit 7 word 1 bit 2 bit 0 bit 1 bit 7 rx/dt write to txreg reg txif bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrgl = 0 , continuous transmission of two 8-bit words. pin tx/ck pin tx/ck pin (sckp = 0 ) (sckp = 1 ) rx/dt pin tx/ck pin write to txreg reg txif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit
pic16(l)f1512/3 ds41624b-page 270 preliminary ? 2012 microchip technology inc. 22.5.1.5 synchronous master reception data is received at the rx/dt pin. the rx/dt pin output driver is automatically disabled when the eusart is configured for synchronous master receive operation. in synchronous mode, reception is enabled by setting either the single receive enable bit (sren of the rcsta register) or the continuous receive enable bit (cren of the rcsta register). when sren is set and cren is clear, only as many clock cycles are generated as there are data bits in a single character. the sren bit is automatically cleared at the completion of one character. when cren is set, clocks are continuously generated until cren is cleared. if cren is cleared in the middle of a character the ck clock stops immediately and the partial charac- ter is discarded. if sren and cren are both set, then sren is cleared at the completion of the first character and cren takes precedence. to initiate reception, set either sren or cren. data is sampled at the rx/dt pin on the trailing edge of the tx/ck clock pin and is shifted into the receive shift register (rsr). when a complete character is received into the rsr, the rcif bit is set and the character is automatically transferred to the two character receive fifo. the least significant eight bits of the top character in the receive fifo are available in rcreg. the rcif bit remains set as long as there are unread characters in the receive fifo. 22.5.1.6 slave clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device configured as a slave receives the clock on the tx/ck line. the tx/ck pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. one data bit is transferred for each clock cycle. only as many clock cycles should be received as there are data bits. 22.5.1.7 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before rcreg is read to access the fifo. when this happens the oerr bit of the rcsta register is set. previous data in the fifo will not be overwritten. the two characters in the fifo buffer can be read, however, no additional characters will be received until the error is cleared. the oerr bit can only be cleared by clearing the overrun condition. if the overrun error occurred when the sren bit is set and cren is clear then the error is cleared by reading rcreg. if the overrun occurred when the cren bit is set then the error condition is cleared by either clearing the cren bit of the rcsta register or by clearing the spen bit which resets the eusart. 22.5.1.8 receiving 9-bit characters the eusart supports 9-bit character reception. when the rx9 bit of the rcsta register is set the eusart will shift 9-bits into the rsr for each character received. the rx9d bit of the rcsta register is the ninth, and most significant, data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the eight least significant bits from the rcreg. 22.5.1.9 synchronous master reception set-up: 1. initialize the spbrgh, spbrgl register pair for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. clear the ansel bit for the rx pin (if applicable). 3. enable the synchronous master serial port by setting bits sync, spen and csrc. 4. ensure bits cren and sren are clear. 5. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 6. if 9-bit reception is desired, set bit rx9. 7. start reception by setting the sren bit or for continuous reception, set the cren bit. 8. interrupt flag bit rcif will be set when reception of a character is complete. an interrupt will be generated if the enable bit rcie was set. 9. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. read the 8-bit received data by reading the rcreg register. 11. if an overrun error occurs, clear the error by either clearing the cren bit of the rcsta register or by clearing the spen bit which resets the eusart. note: if the rx/dt function is on an analog pin, the corresponding ansel bit must be cleared for the receiver to function. note: if the device is configured as a slave and the tx/ck function is on an analog pin, the corresponding ansel bit must be cleared.
? 2012 microchip technology inc. preliminary ds41624b-page 271 pic16(l)f1512/3 figure 22-12: synchronous reception (master mode, sren) table 22-8: summary of registers as sociated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ? wue abden 258 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 rcreg eusart receive data register 252 * rcsta spen rx9 sren cren adden ferr oerr rx9d 257 spbrgl brg<7:0> 259 * spbrgh brg<15:8> 259 * trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 115 txsta csrc tx9 txen sync sendb brgh trmt tx9d 256 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous master reception. * page provides register information. cren bit rx/dt write to bit sren sren bit rcif bit (interrupt) read rcreg ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . tx/ck pin tx/ck pin pin (sckp = 0 ) (sckp = 1 )
pic16(l)f1512/3 ds41624b-page 272 preliminary ? 2012 microchip technology inc. 22.5.2 synchronous slave mode the following bits are used to configure the eusart for synchronous slave operation: ? sync = 1 ? csrc = 0 ? sren = 0 (for transmit); sren = 1 (for receive) ? cren = 0 (for transmit); cren = 1 (for receive) ? spen = 1 setting the sync bit of the txsta register configures the device for synchronous operation. clearing the csrc bit of the txsta register configures the device as a slave. clearing the sren and cren bits of the rcsta register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rcsta register enables the eusart. 22.5.2.1 eusart synchronous slave transmit the operation of the synchronous master and slave modes are identical (see section 22.5.1.3 ?synchronous master transmission? ) , except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: 1. the first character will immediately transfer to the tsr register and transmit. 2. the second word will remain in the txreg register. 3. the txif bit will not be set. 4. after the first character has been shifted out of tsr, the txreg register will transfer the second character to the tsr and the txif bit will now be set. 5. if the peie and txie bits are set, the interrupt will wake the device from sleep and execute the next instruction. if the gie bit is also set, the program will call the interrupt service routine. 22.5.2.2 synchronous slave transmission set-up: 1. set the sync and spen bits and clear the csrc bit. 2. clear the ansel bit for the ck pin (if applicable). 3. clear the cren and sren bits. 4. if interrupts are desired, set the txie bit of the pie1 register and the gie and peie bits of the intcon register. 5. if 9-bit transmission is desired, set the tx9 bit. 6. enable transmission by setting the txen bit. 7. if 9-bit transmission is selected, insert the most significant bit into the tx9d bit. 8. start transmission by writing the least significant eight bits to the txreg register. table 22-9: summary of registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ?sckp brg16 ? wue abden 258 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 rcsta spen rx9 sren cren adden ferr oerr rx9d 257 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 115 txreg eusart transmit data register 249 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 256 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave transmission. * page provides register information.
? 2012 microchip technology inc. preliminary ds41624b-page 273 pic16(l)f1512/3 22.5.2.3 eusart synchronous slave reception the operation of the synchronous master and slave modes is identical ( section 22.5.1.5 ?synchronous master reception? ), with the following exceptions: ? sleep ? cren bit is always set, therefore the receiver is never idle ? sren bit, which is a ?don?t care? in slave mode a character may be received while in sleep mode by setting the cren bit prior to entering sleep. once the word is received, the rsr register will transfer the data to the rcreg register. if the rcie enable bit is set, the interrupt generated will wake the device from sleep and execute the next instruction. if the gie bit is also set, the program will branch to the interrupt vector. 22.5.2.4 synchronous slave reception set-up: 1. set the sync and spen bits and clear the csrc bit. 2. clear the ansel bit for both the ck and dt pins (if applicable). 3. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 4. if 9-bit reception is desired, set the rx9 bit. 5. set the cren bit to enable reception. 6. the rcif bit will be set when reception is complete. an interrupt will be generated if the rcie bit was set. 7. if 9-bit mode is enabled, retrieve the most significant bit from the rx9d bit of the rcsta register. 8. retrieve the eight least significant bits from the receive fifo by reading the rcreg register. 9. if an overrun error occurs, clear the error by either clearing the cren bit of the rcsta register or by clearing the spen bit which resets the eusart. table 22-10: summary of registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ?sckp brg16 ? wue abden 258 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 72 pie1 tmr1gie adie rcie txie sspie ccp1ie tmr2ie tmr1ie 73 pir1 tmr1gif adif rcif txif sspif ccp1if tmr2if tmr1if 75 rcreg eusart receive data register 252 * rcsta spen rx9 sren cren adden ferr oerr rx9d 257 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 115 txsta csrc tx9 txen sync sendb brgh trmt tx9d 256 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used for synchronous slave reception. * page provides register information.
pic16(l)f1512/3 ds41624b-page 274 preliminary ? 2012 microchip technology inc. 22.6 eusart operation during sleep the eusart will remain active during sleep only in the synchronous slave mode. all other modes require the system clock and therefore cannot generate the necessary signals to run the transmit or receive shift registers during sleep. synchronous slave mode uses an externally generated clock to run the transmit and receive shift registers. 22.6.1 synchronous receive during sleep to receive during sleep, all the following conditions must be met before entering sleep mode: ? rcsta and txsta control registers must be configured for synchronous slave reception (see section 22.5.2.4 ?synchronous slave reception set-up:? ). ? if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. ? the rcif interrupt flag must be cleared by read- ing rcreg to unload any pending characters in the receive buffer. upon entering sleep mode, the device will be ready to accept data and clocks on the rx/dt and tx/ck pins, respectively. when the data word has been completely clocked in by the external device, the rcif interrupt flag bit of the pir1 register will be set. thereby, waking the processor from sleep. upon waking from sleep, the instruction following the sleep instruction will be executed. if the global interrupt enable (gie) bit of the intcon register is also set, then the interrupt service routine at address 004h will be called. 22.6.2 synchronous transmit during sleep to transmit during sleep, all the following conditions must be met before entering sleep mode: ? rcsta and txsta control registers must be configured for synchronous slave transmission (see section 22.5.2.2 ?synchronous slave transmission set-up:? ). ? the txif interrupt flag must be cleared by writing the output data to the txreg, thereby filling the tsr and transmit buffer. ? if interrupts are desired, set the txie bit of the pie1 register and the peie bit of the intcon register. ? interrupt enable bits txie of the pie1 register and peie of the intcon register must set. upon entering sleep mode, the device will be ready to accept clocks on tx/ck pin and transmit data on the rx/dt pin. when the data word in the tsr has been completely clocked out by the external device, the pending byte in the txreg will transfer to the tsr and the txif flag will be set. thereby, waking the processor from sleep. at this point, the txreg is available to accept another character for transmission, which will clear the txif flag. upon waking from sleep, the instruction following the sleep instruction will be executed. if the global interrupt enable (gie) bit is also set then the interrupt service routine at address 0004h will be called.
? 2012 microchip technology inc. preliminary ds41624b-page 275 pic16(l)f1512/3 23.0 in-circuit serial programming? (icsp?) icsp? programming allows customers to manufacture circuit boards with unprogrammed devices. programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. five pins are needed for icsp? programming: ? icspclk ? icspdat ?mclr /v pp ?v dd ?v ss in program/verify mode the program memory, user ids and the configuration words are programmed through serial communications. the icspdat pin is a bidirectional i/o used for transferring the serial data and the icspclk pin is the clock input. for more information on icsp? refer to the ? pic16(l)f151x/152x memory programming specification ? (ds41442). 23.1 high-voltage programming entry mode the device is placed into high-voltage programming entry mode by holding the icspclk and icspdat pins low then raising the voltage on mclr /v pp to v ihh . 23.2 low-voltage programming entry mode the low-voltage programming entry mode allows the pic16(l)f151x devices to be programmed using v dd only, without high voltage. when the lvp bit of configuration words is set to ? 1 ?, the low-voltage icsp programming entry is enabled. to disable the low-voltage icsp mode, the lvp bit must be programmed to ? 0 ?. entry into the low-voltage programming entry mode requires the following steps: 1. mclr is brought to v il . 2. a 32-bit key sequence is presented on icspdat, while clocking icspclk. once the key sequence is complete, mclr must be held at v il for as long as program/verify mode is to be maintained. if low-voltage programming is enabled (lvp = 1 ), the mclr reset function is automatically enabled and cannot be disabled. see section 6.3 ?low-power brown-out reset (lpbor)? for more information. the lvp bit can only be reprogrammed to ? 0 ? by using the high-voltage programming mode. 23.3 common programming interfaces connection to a target device is typically done through an icsp? header. a commonly found connector on development tools is the rj-11 in the 6p6c (6-pin, 6 connector) configuration. see figure 23-1 . figure 23-1: icd rj-11 style connector interface 1 2 3 4 5 6 target bottom side pc board v pp /mclr v ss icspclk v dd icspdat nc pin description* 1 = v pp /mclr 2 = v dd target 3 = v ss (ground) 4 = icspdat 5 = icspclk 6 = no connect
pic16(l)f1512/3 ds41624b-page 276 preliminary ? 2012 microchip technology inc. another connector often found in use with the pickit? programmers is a standard 6-pin header with 0.1 inch spacing. refer to figure 23-2 . figure 23-2: pickit? programme r style connector interface 1 2 3 4 5 6 * the 6-pin header (0.100" spacing) accepts 0.025" square pins. pin description* 1 = v pp /mclr 2 = v dd target 3 = v ss (ground) 4 = icspdat 5 = icspclk 6 = no connect pin 1 indicator
? 2012 microchip technology inc. preliminary ds41624b-page 277 pic16(l)f1512/3 for additional interface recommendations, refer to your specific device programmer manual prior to pcb design. it is recommended that isolation devices be used to separate the programming pins from other circuitry. the type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. see figure 23-3 for more information. figure 23-3: typical connect ion for icsp? programming v dd v pp v ss external device to be data clock v dd mclr /v pp v ss icspdat icspclk * * * to normal connections * isolation devices (as required). programming signals programmed v dd
pic16(l)f1512/3 ds41624b-page 278 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds41624b-page 279 pic16(l)f1512/3 24.0 instruction set summary each instruction is a 14-bit word containing the operation code (opcode) and all required operands. the opcodes are broken into three broad categories. ? byte oriented ? bit oriented ? literal and control the literal and control category contains the most var- ied instruction word format. table 24-3 lists the instructions recognized by the mpasm tm assembler. all instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: ? subroutine takes two cycles ( call , callw ) ? returns from interrupts or subroutines take two cycles ( return , retlw , retfie ) ? program branching takes two cycles ( goto , bra , brw , btfss , btfsc , decfsz , incsfz ) ? one additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. one instruction cycle consists of four oscillator cycles; for an oscillator frequency of 4 mhz, this gives a nominal instruction execution rate of 1 mhz. all instruction examples use the format ? 0xhh ? to represent a hexadecimal number, where ? h ? signifies a hexadecimal digit. 24.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion, or the destination designator ?d?. a read operation is performed on a register even if the instruction writes to that register. table 24-1: opcode field descriptions table 24-2: abbreviation descriptions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w , d = 1 : store result in file register f. default is d = 1. n fsr or indf number. (0-1) mm pre-post increment-decrement mode selection field description pc program counter to time-out bit c carry bit dc digit carry bit z zero bit pd power-down bit
pic16(l)f1512/3 ds41624b-page 280 preliminary ? 2012 microchip technology inc. figure 24-1: general format for instructions byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only movlp instruction only 13 5 4 0 opcode k (literal) k = 5-bit immediate value movlb instruction only 13 9 8 0 opcode k (literal) k = 9-bit immediate value bra instruction only fsr offset instructions 13 7 6 5 0 opcode n k (literal) n = appropriate fsr fsr increment instructions 13 7 6 0 opcode k (literal) k = 7-bit immediate value 13 3 2 1 0 opcode n m (mode) n = appropriate fsr m = 2-bit mode value k = 6-bit immediate value 13 0 opcode opcode only
? 2012 microchip technology inc. preliminary ds41624b-page 281 pic16(l)f1512/3 table 24-3: instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf asrf lslf lsrf clrf clrw comf decf incf iorwf movf movwf rlf rrf subwf subwfb swapf xorwf f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d add w and f add with carry w and f and w with f arithmetic right shift logical left shift logical right shift clear f clear w complement f decrement f increment f inclusive or w with f move f move w to f rotate left f through carry rotate right f through carry subtract w from f subtract with borrow w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z c, dc, z z c, z c, z c, z z z z z z z z c c c, dc, z c, dc, z z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 byte oriented skip operations decfsz incfsz f, d f, d decrement f, skip if 0 increment f, skip if 0 1(2) 1(2) 00 00 1011 1111 dfff dfff ffff ffff 1, 2 1, 2 bit-oriented file register operations bcf bsf f, b f, b bit clear f bit set f 1 1 01 01 00bb 01bb bfff bfff ffff ffff 2 2 bit-oriented skip operations btfsc btfss f, b f, b bit test f, skip if clear bit test f, skip if set 1 (2) 1 (2) 01 01 10bb 11bb bfff bfff ffff ffff 1, 2 1, 2 literal operations addlw andlw iorlw movlb movlp movlw sublw xorlw k k k k k k k k add literal and w and literal with w inclusive or literal with w move literal to bsr move literal to pclath move literal to w subtract w from literal exclusive or literal with w 1 1 1 1 1 1 1 1 11 11 11 00 11 11 11 11 1110 1001 1000 0000 0001 0000 1100 1010 kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z z z c, dc, z z note 1: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 2: if this instruction addresses an indf register and the msb of the corresponding fsr is set, this instruction will require one additional instruction cycle.
pic16(l)f1512/3 ds41624b-page 282 preliminary ? 2012 microchip technology inc. table 24-3: instruction set (continued) mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb control operations bra brw call callw goto retfie retlw return k ? k ? k k k ? relative branch relative branch with w call subroutine call subroutine with w go to address return from interrupt return with literal in w return from subroutine 2 2 2 2 2 2 2 2 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 inherent operations clrwdt nop option reset sleep tris ? ? ? ? ? f clear watchdog timer no operation load option_reg register with w software device reset go into standby mode load tris register with w 1 1 1 1 1 1 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 0000 0010 0001 0011 0fff to , pd to , pd c-compiler optimized addfsr moviw movwi n, k n mm k[n] n mm k[n] add literal k to fsrn move indirect fsrn to w with pre/post inc/dec modifier, mm move indfn to w, indexed indirect. move w to indirect fsrn with pre/post inc/dec modifier, mm move w to indfn, indexed indirect. 1 1 1 1 1 11 00 11 00 11 0001 0000 1111 0000 1111 0nkk 0001 0nkk 0001 1nkk kkkk 0nmm kkkk 1nmm kkkk z z 2, 3 2 2, 3 2 note 1: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 2: if this instruction addresses an indf register and the msb of the corresponding fsr is set, this instruction will require one additional instruction cycle. 3: see table in the moviw and movwi instruction descriptions.
? 2012 microchip technology inc. preliminary ds41624b-page 283 pic16(l)f1512/3 24.2 instruction descriptions addfsr add literal to fsrn syntax: [ label ] addfsr fsrn, k operands: -32 ? k ? 31 n ? [ 0, 1] operation: fsr(n) + k ? fsr(n) status affected: none description: the signed 6-bit literal ?k? is added to the contents of the fsrnh:fsrnl register pair. fsrn is limited to the range 0000h - ffffh. moving beyond these bounds will cause the fsr to wrap-around. addlw add literal and w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? (w) status affected: c, dc, z description: the contents of the w register are added to the eight-bit literal ?k? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) + (f) ? (destination) status affected: c, dc, z description: add the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. addwfc add w and carry bit to f syntax: [ label ] addwfc f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (w) + (f) + (c) ? dest status affected: c, dc, z description: add w, the carry flag and data mem- ory location ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in data memory location ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. (k) ? (w) status affected: z description: the contents of w register are and?ed with the eight-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) .and. (f) ? (destination) status affected: z description: and the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. asrf arithmetic right shift syntax: [ label ] asrf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (f<7>) ? dest<7> (f<7:1>) ? dest<6:0>, (f<0>) ? c, status affected: c, z description: the contents of register ?f? are shifted one bit to the right through the carry flag. the msb remains unchanged. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. register f c
pic16(l)f1512/3 ds41624b-page 284 preliminary ? 2012 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 0 ? (f) status affected: none description: bit ?b? in register ?f? is cleared. bra relative branch syntax: [ label ] bra label [ label ] bra $+k operands: -256 ? label - pc + 1 ? 255 -256 ? k ? 255 operation: (pc) + 1 + k ? pc status affected: none description: add the signed 9-bit literal ?k? to the pc. since the pc will have incre- mented to fetch the next instruction, the new address will be pc + 1 + k. this instruction is a two-cycle instruc- tion. this branch has a limited range. brw relative branch with w syntax: [ label ] brw operands: none operation: (pc) + (w) ? pc status affected: none description: add the contents of w (unsigned) to the pc. since the pc will have incre- mented to fetch the next instruction, the new address will be pc + 1 + (w). this instruction is a two-cycle instruc- tion. bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 1 ? (f) status affected: none description: bit ?b? in register ?f? is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, the next instruction is executed. if bit ?b?, in register ?f?, is ? 0 ?, the next instruction is discarded, and a nop is executed instead, making this a 2-cycle instruction. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 127 0 ? b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, the next instruction is executed. if bit ?b? is ? 1 ?, then the next instruction is discarded and a nop is executed instead, making this a 2-cycle instruction.
? 2012 microchip technology inc. preliminary ds41624b-page 285 pic16(l)f1512/3 call call subroutine syntax: [ label ] call k operands: 0 ? k ? 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<6:3>) ? pc<14:11> status affected: none description: call subroutine. first, return address (pc + 1) is pushed onto the stack. the eleven-bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a two-cycle instruc- tion. callw subroutine call with w syntax: [ label ] callw operands: none operation: (pc) +1 ? tos, (w) ? pc<7:0>, (pclath<6:0>) ?? pc<14:8> status affected: none description: subroutine call with w. first, the return address (pc + 1) is pushed onto the return stack. then, the con- tents of w is loaded into pc<7:0>, and the contents of pclath into pc<14:8>. callw is a two-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 127 operation: 00h ? (f) 1 ? z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd description: clrwdt instruction resets the watch- dog timer. it also resets the prescaler of the wdt. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f ) ? (destination) status affected: z description: the contents of register ?f? are complemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
pic16(l)f1512/3 ds41624b-page 286 preliminary ? 2012 microchip technology inc. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none description: the contents of register ?f? are decre- mented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, then a nop is executed instead, making it a 2-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 2047 operation: k ? pc<10:0> pclath<6:3> ? pc<14:11> status affected: none description: goto is an unconditional branch. the eleven-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a two-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination) status affected: z description: the contents of register ?f? are incre- mented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none description: the contents of register ?f? are incre- mented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, a nop is executed instead, making it a 2-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? (w) status affected: z description: the contents of the w register are or?ed with the eight-bit literal ?k?. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .or. (f) ? (destination) status affected: z description: inclusive or the w register with register ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?.
? 2012 microchip technology inc. preliminary ds41624b-page 287 pic16(l)f1512/3 lslf logical left shift syntax: [ label ] lslf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (f<7>) ? c (f<6:0>) ? dest<7:1> 0 ? dest<0> status affected: c, z description: the contents of register ?f? are shifted one bit to the left through the carry flag. a ? 0 ? is shifted into the lsb. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. lsrf logical right shift syntax: [ label ] lsrf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: 0 ? dest<7> (f<7:1>) ? dest<6:0>, (f<0>) ? c, status affected: c, z description: the contents of register ?f? are shifted one bit to the right through the carry flag. a ? 0 ? is shifted into the msb. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. register f 0 c register f c 0 movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) ? (dest) status affected: z description: the contents of register f is moved to a destination dependent upon the status of d. if d = 0 , destination is w register. if d = 1 , the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register z= 1
pic16(l)f1512/3 ds41624b-page 288 preliminary ? 2012 microchip technology inc. moviw move indfn to w syntax: [ label ] moviw ++fsrn [ label ] moviw --fsrn [ label ] moviw fsrn++ [ label ] moviw fsrn-- [ label ] moviw k[fsrn] operands: n ? [ 0 , 1 ] mm ? [ 00 , 01 , 10 , 11 ] -32 ? k ? 31 operation: indfn ? w effective address is determined by ? fsr + 1 (preincrement) ? fsr - 1 (predecrement) ? fsr + k (relative offset) after the move, the fsr value will be either: ? fsr + 1 (all increments) ? fsr - 1 (all decrements) ? unchanged status affected: z mode syntax mm preincrement ++fsrn 00 predecrement --fsrn 01 postincrement fsrn++ 10 postdecrement fsrn-- 11 description: this instruction is used to move data between w and one of the indirect registers (indfn). before/after this move, the pointer (fsrn) is updated by pre/post incrementing/decrementing it. note: the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the fsrn. fsrn is limited to the range 0000h - ffffh. incrementing/decrementing it beyond these bounds will cause it to wrap-around. movlb move literal to bsr syntax: [ label ] movlb k operands: 0 ? k ? 15 operation: k ? bsr status affected: none description: the five-bit literal ?k? is loaded into the bank select register (bsr). movlp move literal to pclath syntax: [ label ] movlp k operands: 0 ? k ? 127 operation: k ? pclath status affected: none description: the seven-bit literal ?k? is loaded into the pclath register. movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none description: the eight-bit literal ?k? is loaded into w register. the ?don?t cares? will assemble as ? 0 ?s. words: 1 cycles: 1 example: movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 127 operation: (w) ? (f) status affected: none description: move data from w register to register ?f?. words: 1 cycles: 1 example: movwf option_reg before instruction option_reg = 0xff w = 0x4f after instruction option_reg = 0x4f w = 0x4f
? 2012 microchip technology inc. preliminary ds41624b-page 289 pic16(l)f1512/3 movwi move w to indfn syntax: [ label ] movwi ++fsrn [ label ] movwi --fsrn [ label ] movwi fsrn++ [ label ] movwi fsrn-- [ label ] movwi k[fsrn] operands: n ? [ 0 , 1 ] mm ? [ 00 , 01 , 10 , 11 ] -32 ? k ? 31 operation: w ? indfn effective address is determined by ? fsr + 1 (preincrement) ? fsr - 1 (predecrement) ? fsr + k (relative offset) after the move, the fsr value will be either: ? fsr + 1 (all increments) ? fsr - 1 (all decrements) unchanged status affected: none mode syntax mm preincrement ++fsrn 00 predecrement --fsrn 01 postincrement fsrn++ 10 postdecrement fsrn-- 11 description: this instruction is used to move data between w and one of the indirect registers (indfn). before/after this move, the pointer (fsrn) is updated by pre/post incrementing/decrementing it. note: the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the fsrn. fsrn is limited to the range 0000h - ffffh. incrementing/decrementing it beyond these bounds will cause it to wrap-around. the increment/decrement operation on fsrn will not affect any status bits. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. words: 1 cycles: 1 example: nop option load option_reg register with w syntax: [ label ] option operands: none operation: (w) ? option_reg status affected: none description: move data from w register to option_reg register. words: 1 cycles: 1 example: option before instruction option_reg = 0xff w = 0x4f after instruction option_reg = 0x4f w = 0x4f reset software reset syntax: [ label ] reset operands: none operation: execute a device reset. resets the nri flag of the pcon register. status affected: none description: this instruction provides a way to execute a hardware reset by software.
pic16(l)f1512/3 ds41624b-page 290 preliminary ? 2012 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie k operands: none operation: tos ? pc, 1 ? gie status affected: none description: return from interrupt. stack is poped and top-of-stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a two-cycle instruction. words: 1 cycles: 2 example: retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the eight bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a two-cycle instruction. words: 1 cycles: 2 example: table call table;w contains table ;offset value ? ;w now has table value ? ? addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; ? ? ? retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a two-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c=0 after instruction reg1 = 1110 0110 w = 1100 1100 c=1 register f c
? 2012 microchip technology inc. preliminary ds41624b-page 291 pic16(l)f1512/3 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. sleep enter sleep mode syntax: [ label ]sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its pres- caler are cleared. the processor is put into sleep mode with the oscillator stopped. register f c sublw subtract w from literal syntax: [ label ]sublw k operands: 0 ?? k ?? 255 operation: k - (w) ??? w) status affected: c, dc, z description: the w register is subtracted (2?s complement method) from the eight-bit literal ?k?. the result is placed in the w register. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 127 d ? [ 0 , 1 ] operation: (f) - (w) ??? destination) status affected: c, dc, z description: subtract (2?s complement method) w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f. subwfb subtract w from f with borrow syntax: subwfb f {,d} operands: 0 ? f ? 127 d ? [0,1] operation: (f) ? (w) ? (b ) ?? dest status affected: c, dc, z description: subtract w and the borrow flag (carry) from register ?f? (2?s comple- ment method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. c = 0 w ? k c = 1 w ? k dc = 0 w<3:0> ? k<3:0> dc = 1 w<3:0> ? k<3:0> c = 0 w ? f c = 1 w ? f dc = 0 w<3:0> ? f<3:0> dc = 1 w<3:0> ? f<3:0>
pic16(l)f1512/3 ds41624b-page 292 preliminary ? 2012 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none description: the upper and lower nibbles of regis- ter ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in register ?f?. tris load tris register with w syntax: [ label ] tris f operands: 5 ? f ? 7 operation: (w) ? tris register ?f? status affected: none description: move data from w register to tris register. when ?f? = 5, trisa is loaded. when ?f? = 6, trisb is loaded. when ?f? = 7, trisc is loaded. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z description: the contents of the w register are xor?ed with the eight-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .xor. (f) ??? destination) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
? 2012 microchip technology inc. preliminary ds41624b-page 293 pic16(l)f1512/3 25.0 electrical specifications absolute maximum ratings (?) ambient temperature under bias................................................................................................. ...... -40c to +125c storage temperature ............................................................................................................ ............ -65c to +150c voltage on v dd with respect to v ss , pic16f1512/3 .......................................................................... -0.3v to +6.5v voltage on v dd with respect to v ss , pic16lf1512/3 ........................................................................ -0.3v to +4.0v voltage on mclr with respect to vss ................................................................................................. -0.3v to +9.0v voltage on all other pins with respect to v ss ........................................................................... -0.3v to (v dd + 0.3v) total power dissipation (1) ............................................................................................................................... 800 mw maximum current out of v ss pin, -40c ? t a ? +85c for industrial............................................................... 340 ma maximum current out of v ss pin, -40c ? t a ? +125c for extended ............................................................ 140 ma maximum current into v dd pin, -40c ? t a ? +85c for industrial.................................................................. 255 ma maximum current into v dd pin, -40c ? t a ? +125c for extended ............................................................... 105 ma clamp current, i k (v pin < 0 or v pin > v dd ) ??????????????????????????????????????????????????????????????? ??????????????????????????????????????????????????? 20 ma maximum output current sunk by any i/o pin..................................................................................... ............... 25 ma maximum output current sourced by any i/o pin .................................................................................. ............ 25 ma note 1: power dissipation is calculated as follows: p dis = v dd x {i dd ? ? i oh } + ? {(v dd ? v oh ) x i oh } + ? (v o l x i ol ). ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure above maximum rating conditions for extended periods may affect device reliability.
pic16(l)f1512/3 ds41624b-page 294 preliminary ? 2012 microchip technology inc. figure 25-1: pic16f1512/3 voltage frequency graph, -40c ? t a ?? +125c figure 25-2: pic16lf1512/3 voltage frequency graph, -40c ? t a ?? +125c note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: refer to table 25-1 for each oscillator mode?s supported frequencies. 0 2.3 frequency (mhz) v dd (v) 420 10 16 5.5 2.5 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: refer to table 25-1 for each oscillator mode?s supported frequencies. 1.8 0 2.5 frequency (mhz) v dd (v) 420 10 16 3.6
? 2012 microchip technology inc. preliminary ds41624b-page 295 pic16(l)f1512/3 25.1 dc characteristics: pic16(l)f1512/3-i/e (industrial, extended) pic16lf1512/3 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f1512/3 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param. no. sym. characteristic min. typ? max. units conditions d001 v dd supply voltage pic16lf1512/3 1.8 2.5 ? ? 3.6 3.6 v v f osc ? 16 mhz: f osc ? 20 mhz d001 pic16f1512/3 2.3 2.5 ? ? 5.5 5.5 v v f osc ? 16 mhz: f osc ? 20 mhz d002* v dr ram data retention voltage (1) pic16lf1512/3 1.5 ? ? v device in sleep mode d002* pic16f1512/3 1.7 ? ? v device in sleep mode v por * power-on reset release voltage ?1.6? v v porr * power-on reset rearm voltage pic16lf1512/3 ? 1.0 ? v pic16f1512/3 ? 1.4 ? v d003 v adfvr fixed voltage reference voltage for adc, initial accuracy -8 ? 6 ? 1.024v, v dd ? 2.5v 2.048v, v dd ? 2.5v 4.096v, v dd ? 4.75v d004* s vdd v dd rise rate to ensure internal power-on reset signal 0.05 ? ? v/ms see section 6.1 ?power-on reset (por)? for details. * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data.
pic16(l)f1512/3 ds41624b-page 296 preliminary ? 2012 microchip technology inc. figure 25-3: por and por rearm with slow rising v dd v dd v por v porr v ss v ss npor t por (3) por rearm note 1: when npor is low, the device is held in reset. 2: t por 1 ? s typical. 3: t vlow 2.7 ? s typical. t vlow (2)
? 2012 microchip technology inc. preliminary ds41624b-page 297 pic16(l)f1512/3 25.2 dc characteristics: pic16(l)f1512/3-i/e (industrial, extended) pic16lf1512/3 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f1512/3 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. units conditions v dd note supply current (i dd ) (1, 2) d010 ? 8.0 14 ? a1.8 f osc = 32 khz lp oscillator mode, -40c ? t a ? +85c ? 12.0 18 ? a3.0 d010 ? 11 23 ? a 2.3 f osc = 32 khz lp oscillator mode, -40c ? t a ? +85c ? 13 24 ? a 3.0 ? 14 26 ? a 5.0 d010a ? 8.0 20 ? a1.8 f osc = 32 khz lp oscillator mode, -40c ? t a ? +125c ? 12.0 30 ? a3.0 d010a ? 11 30 ? a 2.3 f osc = 32 khz lp oscillator mode, -40c ? t a ? +125c ? 13 35 ? a 3.0 ? 14 45 ? a 5.0 d011 ? 60 95 ? a1.8f osc = 1 mhz xt oscillator mode ?110 180 ? a3.0 d011 ? 110 170 ? a 2.3 f osc = 1 mhz xt oscillator mode ? 140 230 ? a 3.0 ? 170 350 ? a 5.0 d012 ? 150 240 ? a1.8f osc = 4 mhz xt oscillator mode ? 260 430 ? a3.0 d012 ? 190 450 ? a 2.3 f osc = 4 mhz xt oscillator mode ? 310 500 ? a 3.0 ? 370 650 ? a 5.0 d013 ? 25 31 ? a1.8f osc = 500 khz ec oscillator low-power mode ?35 50 ? a3.0 d013 ? 25 40 ? a 2.3 f osc = 500 khz ec oscillator low-power mode ? 35 55 ? a 3.0 ? 40 60 ? a 5.0 * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be extended by the formula i r = v dd /2r ext (ma) with r ext in k ??
pic16(l)f1512/3 ds41624b-page 298 preliminary ? 2012 microchip technology inc. 25.2 dc characteristics: pic16(l)f1512/3-i/e (industrial, extended) (continued) pic16lf1512/3 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f1512/3 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. units conditions v dd note supply current (i dd ) (1, 2) d014 ? 120 210 ? a1.8f osc = 4 mhz ec oscillator, medium-power mode ? 210 380 ? a3.0 d014 ? 190 280 ? a 2.3 f osc = 4 mhz ec oscillator, medium-power mode ? 260 380 ? a 3.0 ? 330 480 ? a 5.0 d015 ? 1.2 1.5 ma 3.0 f osc = 20 mhz ec oscillator, high-power mode ?1.3 1.8 ma 3.6 d015 ? 1.2 1.5 ma 3.0 f osc = 20 mhz ec oscillator, high-power mode ? 1.4 2 ma 5.0 d016 ? 2.0 6 ? a1.8f osc = 31 khz lfintosc mode ?4.0 11 ? a3.0 d016 ? 16 25 ? a 2.3 f osc = 31 khz lfintosc mode ? 20 26 ? a 3.0 ? 22 27 ? a 5.0 d017 ? 110 325 ? a1.8f osc = 500 khz hfintosc mode ? 150 400 ? a3.0 d017 ? 290 350 ? a 2.3 f osc = 500 khz hfintosc mode ? 335 400 ? a 3.0 ? 385 430 ? a 5.0 d018 ? 250 600 ? a1.8f osc = 8 mhz hfintosc mode ? 450 1000 ? a3.0 d018 ? 580 750 ? a 2.3 f osc = 8 mhz hfintosc mode ? 730 1000 ? a 3.0 ? 800 1100 ? a 5.0 d019 ? 0.47 1.3 ma 1.8 f osc = 16 mhz hfintosc mode ?0.84 1.5 ma 3.0 d019 ? 0.85 1.3 ma 2.3 f osc = 16 mhz hfintosc mode ? 1.1 1.5 ma 3.0 ? 1.2 1.7 ma 5.0 * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be extended by the formula i r = v dd /2r ext (ma) with r ext in k ??
? 2012 microchip technology inc. preliminary ds41624b-page 299 pic16(l)f1512/3 25.2 dc characteristics: pic16(l)f1512/3-i/e (industrial, extended) (continued) pic16lf1512/3 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f1512/3 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. units conditions v dd note supply current (i dd ) (1, 2) d020 ? 1.0 1.8 ma 3.0 f osc = 20 mhz hs oscillator mode ?1.2 2.1 ma 3.6 d020 ? 1.4 1.7 ma 3.0 f osc = 20 mhz hs oscillator mode ? 1.7 2.1 ma 5.0 d021 ? 150 220 ? a1.8f osc = 4 mhz extrc mode ? 250 380 ? a3.0 d021 ? 200 330 ? a 2.3 f osc = 4 mhz extrc mode ? 280 420 ? a 3.0 ? 350 500 ? a 5.0 * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v dd ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: for rc oscillator configurations, current through r ext is not included. the current through the resistor can be extended by the formula i r = v dd /2r ext (ma) with r ext in k ??
pic16(l)f1512/3 ds41624b-page 300 preliminary ? 2012 microchip technology inc. 25.3 dc characteristics: pic16(l)f1512/3-i/e (power-down) pic16lf1512/3 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f1512/3 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. +85c max. +125c units conditions v dd note power-down base current (i pd ) (2),(4) d022 ? 0.02 1.0 8.0 ? a 1.8 wdt, bor, fvr, and sosc disabled, all peripherals inactive ? 0.03 2.0 9.0 ? a3.0 d022 ? 0.30 2.0 11 ? a 2.3 wdt, bor, fvr, and sosc disabled, all peripherals inactive ? 0.40 3.0 12 ? a 3.0 ? 0.50 6 15 ? a 5.0 d023 ? 0.50 6 14 ? a 1.8 lpwdt current (note 1) ?0.80 7 17 ? a3.0 d023 ? 0.50 6 15 ? a 2.3 lpwdt current (note 1) ? 0.77 7 20 ? a 3.0 ? 0.85 8 22 ? a 5.0 d023a ? 8.5 23 25 ? a 1.8 fvr current (note 1) ? 8.5 24 27 ? a3.0 d023a ? 18 26 30 ? a 2.3 fvr current (note 1) ? 19 27 37 ? a 3.0 ? 20 29 45 ? a 5.0 d024 ? 8.0 17 20 ? a 3.0 bor current (note 1) d024 ? 8 17 30 ? a 3.0 bor current (note 1) ? 9 20 40 ? a 5.0 d024a ? 0.30 4 8 ? a 3.0 lpbor current d024a ? 0.30 4 14 ? a 3.0 lpbor current ? 0.45 8 17 ? a 5.0 d025 ? 0.6 5 9 ? a 1.8 sosc current (note 1) ?1.88.5 12 ? a3.0 d025 ? 0.7 6 10 ? a 2.3 sosc current (note 1) ? 3 8.5 20 ? a 3.0 ? 6 10 25 ? a 5.0 d026 ? 0.1 1 9 ? a 1.8 a/d current (note 1, note 3) , no conversion in progress ?0.1 2 10 ? a3.0 * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . 3: a/d oscillator source is f rc . 4: specification for pic16f1512/3 devices assumes that low-power sleep mode is selected, when available, via the vregcon register (see section 8.2.2 ?peripheral usage in sleep? and register 8-1 ).
? 2012 microchip technology inc. preliminary ds41624b-page 301 pic16(l)f1512/3 d026 ? 0.16 1 10 ? a 2.3 a/d current (note 1, note 3) , no conversion in progress ? 0.40 2 11 ? a 3.0 ? 0.50 6 16 ? a 5.0 power-down base current (i pd ) (2),(4) d026a* ? 250 400 410 ? a 1.8 a/d current (note 1, note 3) , conversion in progress ? 260 420 430 ? a3.0 d026a* ? 280 430 440 ? a 2.3 a/d current (note 1, note 3) , conversion in progress ? 300 450 460 ? a 3.0 ? 320 470 480 ? a 5.0 25.3 dc characteristics: pic16(l)f1512/3-i/e (power-down) (continued) pic16lf1512/3 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended pic16f1512/3 standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. device characteristics min. typ? max. +85c max. +125c units conditions v dd note * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral current is the sum of the base i dd or i pd and the additional current consumed when this peripheral is enabled. the peripheral ? current can be determined by subtracting the base i dd or i pd current from this limit. max values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v dd . 3: a/d oscillator source is f rc . 4: specification for pic16f1512/3 devices assumes that low-power sleep mode is selected, when available, via the vregcon register (see section 8.2.2 ?peripheral usage in sleep? and register 8-1 ).
pic16(l)f1512/3 ds41624b-page 302 preliminary ? 2012 microchip technology inc. 25.4 dc characteristics: pic16(l)f1512/3-i/e dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +85c for industrial -40c ? t a ? +125c for extended param no. sym. characteristic min. typ? max. units conditions v il input low voltage i/o port: d030 with ttl buffer ? ? 0.8 v 4.5v ? v dd ? 5.5v d030a ? ? 0.15 v dd v1.8v ? v dd ? 4.5v d031 with schmitt trigger buffer ? ? 0.2 v dd v2.0v ? v dd ? 5.5v with i 2 c? levels ? ? 0.3 v dd v with smbus levels ? ? 0.8 v 2.7v ? v dd ? 5.5v d032 mclr , osc1 (rc mode) (1) ??0.2v dd v d033 osc1 (hs mode) ? ? 0.3 v dd v v ih input high voltage i/o ports: ? ? d040 with ttl buffer 2.0 ? ? v 4.5v ? v dd ?? 5.5v d040a 0.25 v dd + 0.8 ??v1.8v ? v dd ? 4.5v d041 with schmitt trigger buffer 0.8 v dd ??v2.0v ? v dd ? 5.5v with i 2 c? levels 0.7 v dd ??v with smbus levels 2.1 ? ? v 2.7v ? v dd ? 5.5v d042 mclr 0.8 v dd ??v d043a osc1 (hs mode) 0.7 v dd ??v d043b osc1 (rc mode) 0.9 v dd ??vv dd ? 2.0v (note 1) i il input leakage current (2) d060 i/o ports ? 5 5 125 1000 na na v ss ? v pin ? v dd , pin at high- impedance at 85c 125c d061 mclr (3) ? 50 200nav ss ? v pin ? v dd at 85c i pur weak pull-up current d070* 25 25 100 140 200 300 ? a v dd = 3.3v, v pin = v ss v dd = 5.0v, v pin = v ss v ol output low voltage (4) d080 i/o ports ??0.6v i ol = 8ma, v dd = 5v i ol = 6ma, v dd = 3.3v i ol = 1.8ma, v dd = 1.8v v oh output high voltage (4) d090 i/o ports v dd - 0.7 ? ? v i oh = 3.5ma, v dd = 5v i oh = 3ma, v dd = 3.3v i oh = 1ma, v dd = 1.8v capacitive loading specs on output pins d101* cosc2 osc2 pin ? ? 15 pf in xt, hs and lp modes when external clock is used to drive osc1 d101a* c io all i/o pins ? ? 50 pf * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in rc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended to use an external clock in rc mode. 2: negative current is defined as current sourced by the pin. 3: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 4: including osc2 in clkout mode.
? 2012 microchip technology inc. preliminary ds41624b-page 303 pic16(l)f1512/3 25.5 memory programming requirements dc characteristics standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions program memory programming specifications d110 v ihh voltage on mclr /v pp /ra5 pin 8.0 ? 9.0 v (note 2, note 3) d111 i ddp supply current during programming ??10ma d112 v dd for bulk erase 2.7 ? v dd max. v d113 v pew v dd for write or row erase v dd min. ?v dd max. v d114 i pppgm current on mclr /v pp during erase/ write ??1.0ma d115 i ddpgm current on v dd during erase/write ? 5.0 ma program flash memory d121 e p cell endurance 10k ? ? e/w -40 ? c to +85 ? c ( note 1 ) d122 v prw v dd for read/write v dd min. ?v dd max. v d123 t iw self-timed write cycle time ? 2 2.5 ms d124 t retd characteristic retention ? 40 ? year provided no other specifications are violated ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: self-write and block erase. 2: required only if single-supply programming is disabled. 3: the mplab ? icd 2 does not support variable v pp output. circuitry to limit the mplab icd 2 v pp voltage must be placed between the mplab icd 2 and target system when programming or debugging with the mplab icd 2.
pic16(l)f1512/3 ds41624b-page 304 preliminary ? 2012 microchip technology inc. 25.6 thermal considerations standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic typ. units conditions th01 ? ja thermal resistance junction to ambient 80 ? c/w 28-pin soic package 60 ? c/w 28-pin spdip package 90 ? c/w 28-pin ssop package 27.5 ? c/w 28-pin uqfn package th02 ? jc thermal resistance junction to case 24 ? c/w 28-pin soic package 31.4 ? c/w 28-pin spdip package 24 ? c/w 28-pin ssop package 24 ? c/w 28-pin uqfn package th03 t jmax maximum junction temperature 150 ? c th04 pd power dissipation ? w pd = p internal + p i / o th05 p internal internal power dissipation ? w p internal = i dd x v dd (1) th06 p i / o i/o power dissipation ? w p i / o = ? (i ol * v ol ) + ? (i oh * (v dd - v oh )) th07 p der derated power ? w p der = pd max (t j - t a )/ ? ja (2) legend: tbd = to be determined note 1: i dd is current to run the chip alone without driving any load on the output pins. 2: t a = ambient temperature. 3: t j = junction temperature.
? 2012 microchip technology inc. preliminary ds41624b-page 305 pic16(l)f1512/3 25.7 timing parameter symbology the timing parameter symbols have been created with one of the following formats: figure 25-4: load conditions 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc osc1 ck clkout rd rd cs cs rw rd or wr di sdix sc sckx do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance v ss c l legend: c l = 50 pf for all pins, 15 pf for osc2 output load condition pin
pic16(l)f1512/3 ds41624b-page 306 preliminary ? 2012 microchip technology inc. 25.8 ac characteristics: pic16(l)f1512/3-i/e figure 25-5: clock timing table 25-1: clock oscillator timing requirements osc1/clkin osc2/clkout q4 q1 q2 q3 q4 q1 os02 os03 os04 os04 osc2/clkout (lp,xt,hs modes) (clkout mode) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions os01 f osc external clkin frequency (1) dc ? 0.5 mhz ec oscillator mode (low) dc ? 4 mhz ec oscillator mode (medium) dc ? 20 mhz ec oscillator mode (high) oscillator frequency (1) ? 32.768 ? khz lp oscillator mode 0.1 ? 4 mhz xt oscillator mode 1 ? 4 mhz hs oscillator mode 1 ? 20 mhz hs oscillator mode, v dd ? 2.7v dc ? 4 mhz rc oscillator mode, v dd ? 2.0v os02 t osc external clkin period (1) 27 ? ?? s lp oscillator mode 250 ? ? ns xt oscillator mode 50 ? ? ns hs oscillator mode 50 ? ? ns ec oscillator mode oscillator period (1) ? 30.5 ? ? s lp oscillator mode 250 ? 10,000 ns xt oscillator mode 50 ? 1,000 ns hs oscillator mode 250 ? ? ns rc oscillator mode os03 t cy instruction cycle time (1) 125 ? dc ns t cy = f osc /4 os04* tosh, tosl external clkin high, external clkin low 2?? ? s lp oscillator 100 ? ? ns xt oscillator 20 ? ? ns hs oscillator os05* tosr, tosf external clkin rise, external clkin fall 0? ? ns lp oscillator 0? ? ns xt oscillator 0? ? ns hs oscillator * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at ?min? values wi th an external clock applied to osc1 pin. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices.
? 2012 microchip technology inc. preliminary ds41624b-page 307 pic16(l)f1512/3 table 25-2: oscillator parameters figure 25-6: clkout and i/o timing standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic freq. tolerance min. typ? max. units conditions os08 hf osc internal calibrated hfintosc frequency (2) ? 2% ? 4% ? 4% to ? 8% ? 4% to ? 12% ? ? ? ? 16.0 16.0 16.0 16.0 ? ? ? ? mhz mhz mhz mhz 25c; 3.2v 0c ? t a ? +85c 2.3v ? v dd ? 5.5v -40c ? t a ? +125c 2.0v ? v dd ? 5.5v -40c ? t a ? +125c 1.8v ? v dd ? 5.5v os09 lf osc internal lfintosc frequency ? ? 31 ? khz os10* t iosc st hfintosc wake-up from sleep start-up time ? ? 3 8 ? s * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwi se stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator ty pe under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected cur- rent consumption. all devices are tested to operate at ?min ? values with an external clock applied to the osc1 pin. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. 2: to ensure these oscillator frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended. 3: by design. f osc clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 os11 os19 os13 os15 os18, os19 os20 os21 os17 os16 os14 os12 os18 old value new value write fetch read execute cycle
pic16(l)f1512/3 ds41624b-page 308 preliminary ? 2012 microchip technology inc. table 25-3: clkout and i/o timing parameters figure 25-7: reset, watchdog timer, os cillator start-up timer and power-up timer timing standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions os11 tosh2ckl f osc ? to clkout ? (1) ??70nsv dd = 3.3-5.0v os12 tosh2ckh f osc ? to clkout ? (1) ??72nsv dd = 3.3-5.0v os13 tckl2iov clkout ? to port out valid (1) ??20ns os14 tiov2ckh port input valid before clkout ? (1) t osc + 200 ns ? ? ns os15 tosh2iov fosc ? (q1 cycle) to port out valid ? 50 70* ns v dd = 3.3-5.0v os16 tosh2ioi fosc ? (q2 cycle) to port input invalid (i/o in hold time) 50 ? ? ns v dd = 3.3-5.0v os17 tiov2osh port input valid to fosc ?? (q2 cycle) (i/o in setup time) 20 ? ? ns os18 tior port output rise time ? ? 40 15 72 32 ns v dd = 1.8v v dd = 3.3-5.0v os19 tiof port output fall time ? ? 28 15 55 30 ns v dd = 1.8v v dd = 3.3-5.0v os20* tinp int pin input high or low time 25 ? ? ns os21* tioc interrupt-on-change new input level time 25 ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25 ? c unless otherwise stated. note 1: measurements are taken in rc mode where clkout output is 4 x t osc . v dd mclr internal por pwrt time-out osc start-up time internal reset (1) watchdog timer 33 32 30 31 34 i/o pins 34 note 1: asserted low. reset (1)
? 2012 microchip technology inc. preliminary ds41624b-page 309 pic16(l)f1512/3 figure 25-8: brown-out rese t timing and characteristics v bor v dd (device in brown-out reset) (device not in brown-out reset) 33 (1) note 1: 64 ms delay only if pwrte bit in the configuration words is programmed to ? 0 ?. 2 ms delay if pwrte = 0 and vregen = 1 . reset (due to bor) v bor and v hyst 37
pic16(l)f1512/3 ds41624b-page 310 preliminary ? 2012 microchip technology inc. table 25-4: reset, watchdog timer, oscill ator start-up timer, power-up timer and brown-out reset parameters standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions 30 t mc lmclr pulse width (low) 2 ? ? ? s 31 t wdtlp low-power watchdog timer time-out period 10 16 27 ms v dd = 3.3v-5v, 1:16 prescaler used 32 t ost oscillator start-up timer period (1), (2) ? 1024 ? tosc (note 3) 33* t pwrt power-up timer period, pwrte = 0 40 65 140 ms 34* t ioz i/o high-impedance from mclr low or watchdog timer reset ??2.0 ? s 35 v bor brown-out reset voltage 2.58 2.35 1.80 2.70 2.45 1.9 2.85 2.57 2.11 vborv = 2.7v bor = 2.45v for f devices only borv = 1.9v for lf devices only 35a v lpbor low-power brown-out 1.8 2.1 2.5 v lpbor = 1 36* v hyst brown-out reset hysteresis 0 25 60 mv -40c to +85c 37* t bordc brown-out reset dc response time 1335 ? sv dd ? v bor * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. legend: tbd = to be determined note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. all devices ar e tested to operate at ?min? values with an external clock applied to the osc1 pin. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices. 2: by design. 3: period of the slower clock. 4: to ensure these voltage tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended.
? 2012 microchip technology inc. preliminary ds41624b-page 311 pic16(l)f1512/3 figure 25-9: timer0 and timer1 external clock timings table 25-5: timer0 and timer1 external clock requirements standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param no. sym. characteristic min. typ? max. units conditions 40* t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 41* t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 42* t t 0p t0cki period greater of: 20 or t cy + 40 n ? ? ns n = prescale value (2, 4, ..., 256) 45* t t 1h t1cki high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 46* t t 1l t1cki low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 47* t t 1p t1cki input period synchronous greater of: 30 or t cy + 40 n ? ? ns n = prescale value (1, 2, 4, 8) asynchronous 60 ? ? ns 48 f t 1 secondary oscillator input frequency range (oscillator enabled by setting bit t1oscen) 32.4 32.768 33.1 khz 49* tckez tmr 1 delay from external clock edge to timer increment 2 t osc ?7 t osc ? timers in sync mode * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. t0cki t1cki 40 41 42 45 46 47 49 tmr0 or tmr1
pic16(l)f1512/3 ds41624b-page 312 preliminary ? 2012 microchip technology inc. figure 25-10: capture/com pare/pwm timings (ccp) table 25-6: capture/compare/pwm requirements (ccp) table 25-7: pic16(l)f1512/3 a/d converter (adc) characteristics : standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions cc01* tccl ccp input low time no prescaler 0.5t cy + 20 ? ? ns with prescaler 20 ? ? ns cc02* tcch ccp input high time no prescaler 0.5t cy + 20 ? ? ns with prescaler 20 ? ? ns cc03* tccp ccp input period 3t cy + 40 n ? ? ns n = prescale value (1, 4 or 16) * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. standard operating conditions (unless otherwise stated) operating temperature tested at 25c param no. sym. characteristic min. typ? max. units conditions ad01 n r resolution ? ? 10 bit ad02 e il integral error ? ? 1.25 lsb v ref = 3.0v ad03 e dl differential error ? ? 1 lsb no missing codes v ref = 3.0v ad04 e off offset error ? ? 2.5 lsb v ref = 3.0v ad05 e gn gain error ? ? 2.0 lsb v ref = 3.0v ad06 v ref reference voltage (3) 1.8 ? v dd vv ref = (v ref + minus v ref -) ( note 5 ) ad07 v ain full-scale range v ss ?v ref v ad08 z ain recommended impedance of analog voltage source ?? 10k ? can go higher if external 0.01 ? f capacitor is present on input pin. * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: total absolute error includes integral, differential, offset and gain errors. 2: the a/d conversion result never decreases with an increase in the input voltage and has no missing codes. 3: adc v ref is from external v ref , v dd pin or fv ref , whichever is selected as reference input. 4: when adc is off, it will not consume any current other than leakage current. the power-down current specification includes any such leakage from the adc module. 5: fvr voltage selected must be 2.048v or 4.096v. note: refer to figure 25-4 for load conditions. (capture mode) cc01 cc02 cc03 ccp
? 2012 microchip technology inc. preliminary ds41624b-page 313 pic16(l)f1512/3 table 25-8: pic16(l)f1512/3 a/d conversion requirements figure 25-11: pic16(l)f1512/3 a/d conversion timing (normal mode) standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions ad130* t ad a/d clock period 1.0 ? 9.0 ? st osc -based a/d internal rc oscillator period 1.0 1.6 6.0 ? s adcs<1:0> = 11 (adrc mode) ad131 t cnv conversion time (not including acquisition time) (1) ?11?t ad set go/done bit to conversion complete ad132* t acq acquisition time ? 5.0 ? ? s * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the adres register may be read on the following t cy cycle. ad131 ad130 bsf adcon0, go q4 a/d clk a/d data adresx adif go sample old_data sampling stopped done new_data 765 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. 1 t cy 4 ad134 (t osc /2 (1) ) 1 t cy ad132
pic16(l)f1512/3 ds41624b-page 314 preliminary ? 2012 microchip technology inc. figure 25-12: pic16(l)f1512/3 a/d conversion timing (sleep mode) table 25-9: pic16(l)f1512/3 low dro pout (ldo) regulator characteristics : figure 25-13: usart synchronous transmission (master/slave) timing standard operating conditions (unless otherwise stated) operating temperature -40c ? t a ? +125c param no. sym. characteristic min. typ? max. units conditions ld001 ldo regulation voltage ? 3.4 ? v ld002 ldo external capacitor 0.1 ? 1 ? f * these parameters are characterized but not tested. ? data in ?typ? column is at 5.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. ad132 ad131 ad130 bsf adcon0, go q4 a/d clk a/d data adresx adif go sample old_data sampling stopped done new_data 7 5 3210 note 1: if the a/d clock source is selected as rc, a time of t cy is added before the a/d clock starts. this allows the sleep instruction to be executed. ad134 4 6 1 t cy (t osc /2 + t cy (1) ) 1 t cy note: refer to figure 25-4 for load conditions. us121 us121 us120 us122 ck dt
? 2012 microchip technology inc. preliminary ds41624b-page 315 pic16(l)f1512/3 table 25-10: usart synchronous tran smission requirements figure 25-14: usart synchrono us receive (master/slave) timing table 25-11: usart synchronous receive requirements standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param. no. symbol characteristic min. max. units conditions us120 t ck h2 dt v sync xmit (m aster and s lave ) clock high to data-out valid 3.0-5.5v ? 80 ns 1.8-5.5v ? 100 ns us121 t ckrf clock out rise time and fall time (master mode) 3.0-5.5v ? 45 ns 1.8-5.5v ? 50 ns us122 t dtrf data-out rise time and fall time 3.0-5.5v ? 45 ns 1.8-5.5v ? 50 ns standard operating conditions (unless otherwise stated) operating temperature -40c ?? t a ?? +125c param. no. symbol characteristic min. max. units conditions us125 t dt v2 ckl sync rcv (m aster and s lave ) data-hold before ck ? (dt hold time) 10 ? ns us126 t ck l2 dtl data-hold after ck ? (dt hold time) 15 ? ns note: refer to figure 25-4 for load conditions. us125 us126 ck dt
pic16(l)f1512/3 ds41624b-page 316 preliminary ? 2012 microchip technology inc. figure 25-15: spi master mode timing (cke = 0 , smp = 0 ) figure 25-16: spi master mode timing (cke = 1 , smp = 1 ) ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp70 sp71 sp72 sp73 sp74 sp75, sp76 sp78 sp79 sp80 sp79 sp78 msb lsb bit 6 - - - - - -1 msb in lsb in bit 6 - - - -1 note: refer to figure 25-4 for load conditions. ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp81 sp71 sp72 sp74 sp75, sp76 sp78 sp80 msb sp79 sp73 msb in bit 6 - - - - - -1 lsb in bit 6 - - - -1 lsb note: refer to figure 25-4 for load conditions.
? 2012 microchip technology inc. preliminary ds41624b-page 317 pic16(l)f1512/3 figure 25-17: spi slav e mode timing (cke = 0 ) figure 25-18: spi slav e mode timing (cke = 1 ) ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp70 sp71 sp72 sp73 sp74 sp75, sp76 sp77 sp78 sp79 sp80 sp79 sp78 msb lsb bit 6 - - - - - -1 msb in bit 6 - - - -1 lsb in sp83 note: refer to figure 25-4 for load conditions. ssx sckx (ckp = 0 ) sckx (ckp = 1 ) sdox sdix sp70 sp71 sp72 sp82 sp74 sp75, sp76 msb bit 6 - - - - - -1 lsb sp77 msb in bit 6 - - - -1 lsb in sp80 sp83 note: refer to figure 25-4 for load conditions.
pic16(l)f1512/3 ds41624b-page 318 preliminary ? 2012 microchip technology inc. table 25-12: spi mode requirements figure 25-19: i 2 c? bus start/stop bits timing param no. symbol characteristic min. typ? max. units conditions sp70* t ss l2 sc h, t ss l2 sc l ss x ? to sckx ? or sckx ? input t cy ??ns sp71* t sc h sckx input high time (slave mode) t cy + 20 ? ? ns sp72* t sc l sckx input low time (slave mode) t cy + 20 ? ? ns sp73* t di v2 sc h, t di v2 sc l setup time of sdix data input to sckx edge 100 ? ? ns sp74* t sc h2 di l, t sc l2 di l hold time of sdix data input to sckx edge 100 ? ? ns sp75* t do r sdo data output rise time 3.0-5.5v ? 10 25 ns 1.8-5.5v ? 25 50 ns sp76* t do f sdox data output fall time ? 10 25 ns sp77* t ss h2 do z ssx ? to sdox output high-impedance 10 ? 50 ns sp78* t sc r sckx output rise time (master mode) 3.0-5.5v ? 10 25 ns 1.8-5.5v ? 25 50 ns sp79* t sc f sckx output fall time (master mode) ? 10 25 ns sp80* t sc h2 do v, t sc l2 do v sdox data output valid after sckx edge 3.0-5.5v ? ? 50 ns 1.8-5.5v ? ? 145 ns sp81* t do v2 sc h, t do v2 sc l sdox data output setup to sckx edge tcy ? ? ns sp82* t ss l2 do v sdox data output valid after ss ? edge ? ? 50 ns sp83* t sc h2 ss h, t sc l2 ss h ssx ?? after sckx edge 1.5t cy + 40 ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note : refer to figure 25-4 for load conditions. sp91 sp92 sp93 sclx sdax start condition stop condition sp90
? 2012 microchip technology inc. preliminary ds41624b-page 319 pic16(l)f1512/3 figure 25-20: i 2 c? bus data timing note: refer to figure 25-4 for load conditions. sp90 sp91 sp92 sp100 sp101 sp103 sp106 sp107 sp109 sp109 sp110 sp102 sclx sdax in sdax out
pic16(l)f1512/3 ds41624b-page 320 preliminary ? 2012 microchip technology inc. table 25-13: i 2 c? bus data requirements param. no. symbol characteristic min. max. units conditions sp100* t high clock high time 100 khz mode 4.0 ? ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy ?? sp101* t low clock low time 100 khz mode 4.7 ? ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy ?? sp102* t r sdax and sclx rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1c b 300 ns c b is specified to be from 10-400 pf sp103* t f sdax and sclx fall time 100 khz mode ? 250 ns 400 khz mode 20 + 0.1c b 250 ns c b is specified to be from 10-400 pf sp106* t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ? s sp107* t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns sp109* t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns sp110* t buf bus free time 100 khz mode 4.7 ? ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ? s sp111 c b bus capacitive loading ? 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of sclx to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c ? bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su : dat ?? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the sclx signal. if such a device does stretch the low period of the sclx sig- nal, it must output the next data bit to the sdax line t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the sclx line is released.
? 2012 microchip technology inc. preliminary ds41624b-page 321 pic16(l)f1512/3 26.0 dc and ac characteristics graphs and charts graphs and charts are not available at this time.
pic16(l)f1512/3 ds41624b-page 322 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds41624b-page 323 pic16(l)f1512/3 27.0 development support the pic ? microcontrollers and dspic ? digital signal controllers are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? ide software ? compilers/assemblers/linkers - mplab c compiler for various device families - hi-tech c ? for various device families - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families ? simulators - mplab sim software simulator ?emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers - mplab icd 3 - pickit? 3 debug express ? device programmers - pickit? 2 programmer - mplab pm3 device programmer ? low-cost demonstration/development boards, evaluation kits, and starter kits 27.1 mplab integrated development environment software the mplab ide software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. the mplab ide is a windows ? operating system-based application that contains: ? a single graphical interface to all debugging tools - simulator - programmer (sold separately) - in-circuit emulator (sold separately) - in-circuit debugger (sold separately) ? a full-featured editor with color-coded context ? a multiple project manager ? customizable data windows with direct edit of contents ? high-level source code debugging ? mouse over variable inspection ? drag and drop variables from source to watch windows ? extensive on-line help ? integration of select third party tools, such as iar c compilers the mplab ide allows you to: ? edit your source files (either c or assembly) ? one-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) ? debug using: - source files (c or assembly) - mixed c and assembly - machine code mplab ide supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. this eliminates the learning curve when upgrading to tools with increased flexibility and power.
pic16(l)f1512/3 ds41624b-page 324 preliminary ? 2012 microchip technology inc. 27.2 mplab c compilers for various device families the mplab c compiler code development systems are complete ansi c compilers for microchip?s pic18, pic24 and pic32 families of microcontrollers and the dspic30 and dspic33 families of digital signal control- lers. these compilers provide powerful integration capabilities, superior code optimization and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. 27.3 hi-tech c for various device families the hi-tech c compiler code development systems are complete ansi c compilers for microchip?s pic family of microcontrollers and the dspic family of digital signal controllers. these compilers provide powerful integration capabilities, omniscient code generation and ease of use. for easy source level debugging, the compilers provide symbol information that is optimized to the mplab ide debugger. the compilers include a macro assembler, linker, pre- processor, and one-step driver, and can run on multiple platforms. 27.4 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code and coff files for debugging. the mpasm assembler features include: ? integration into mplab ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multi-purpose source files ? directives that allow complete control over the assembly process 27.5 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler and the mplab c18 c compiler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 27.6 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic devices. mplab c compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command line interface ? rich directive set ? flexible macro language ? mplab ide compatibility
? 2012 microchip technology inc. preliminary ds41624b-page 325 pic16(l)f1512/3 27.7 mplab sim software simulator the mplab sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic ? dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab sim software simulator fully supports symbolic debugging using the mplab c compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 27.8 mplab real ice in-circuit emulator system mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs pic ? flash mcus and dspic ? flash dscs with the easy-to-use, powerful graphical user interface of the mplab integrated development environment (ide), included with each kit. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in- circuit debugger systems (rj11) or with the new high- speed, noise tolerant, low-voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab ide. in upcoming releases of mplab ide, new devices will be supported, and new features will be added. mplab real ice offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. 27.9 mplab icd 3 in-circuit debugger system mplab icd 3 in-circuit debugger system is micro- chip's most cost effective high-speed hardware debugger/programmer for microchip flash digital sig- nal controller (dsc) and microcontroller (mcu) devices. it debugs and programs pic ? flash microcon- trollers and dspic ? dscs with the powerful, yet easy- to-use graphical user interface of mplab integrated development environment (ide). the mplab icd 3 in-circuit debugger probe is con- nected to the design engineer's pc using a high-speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 27.10 pickit 3 in-circuit debugger/ programmer and pickit 3 debug express the mplab pickit 3 allows debugging and program- ming of pic ? and dspic ? flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab integrated development environment (ide). the mplab pickit 3 is connected to the design engineer's pc using a full speed usb interface and can be connected to the target via an microchip debug (rj-11) connector (compatible with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to imple- ment in-circuit debugging and in-circuit serial pro- gramming?. the pickit 3 debug express include the pickit 3, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software.
pic16(l)f1512/3 ds41624b-page 326 preliminary ? 2012 microchip technology inc. 27.11 pickit 2 development programmer/debugger and pickit 2 debug express the pickit? 2 development programmer/debugger is a low-cost development tool with an easy to use inter- face for programming and debugging microchip?s flash families of microcontrollers. the full featured windows ? programming interface supports baseline (pic10f, pic12f5xx, pic16f5xx), midrange (pic12f6xx, pic16f), pic18f, pic24, dspic30, dspic33, and pic32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many microchip serial eeprom products. with microchip?s powerful mplab integrated development environment (ide) the pickit? 2 enables in-circuit debugging on most pic ? microcon- trollers. in-circuit-debugging runs, halts and single steps the program while the pic microcontroller is embedded in the application. when halted at a break- point, the file registers can be examined and modified. the pickit 2 debug express include the pickit 2, demo board and microcontroller, hookup cables and cdrom with user?s guide, lessons, tutorial, compiler and mplab ide software. 27.12 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages and a modu- lar, detachable socket assembly to support various package types. the icsp? cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an mmc card for file storage and data applications. 27.13 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully func- tional systems. most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demon- stration/development board series of circuits, microchip has a line of evaluation kits and demonstration software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits.
? 2012 microchip technology inc. preliminary ds41624b-page 327 pic16(l)f1512/3 28.0 packaging information 28.1 package marking information legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 28-lead soic (7.50 mm) example yywwnnn xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx pi111 1111 28-lead spdip (.300?) example pic16f1512-e/sp 1110017 28-lead ssop (5.30 mm) example pic16f1512-e/ss 1110017 3 e
pic16(l)f1512/3 ds41624b-page 328 preliminary ? 2012 microchip technology inc. package marking information (continued) 28-lead uqfn (4x4x0.5 mm) example pin 1 pin 1 pi1 111 11 i 3 e
? 2012 microchip technology inc. preliminary ds41624b-page 329 pic16(l)f1512/3 28.2 package details the following sections give the technical details of the packages. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16(l)f1512/3 ds41624b-page 330 preliminary ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012 microchip technology inc. preliminary ds41624b-page 331 pic16(l)f1512/3 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16(l)f1512/3 ds41624b-page 332 preliminary ? 2012 microchip technology inc.

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pic16(l)f1512/3 ds41624b-page 334 preliminary ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012 microchip technology inc. preliminary ds41624b-page 335 pic16(l)f1512/3 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16(l)f1512/3 ds41624b-page 336 preliminary ? 2012 microchip technology inc. note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
? 2012 microchip technology inc. preliminary ds41624b-page 337 pic16(l)f1512/3 appendix a: data sheet revision history revision a (02/2012) original release (02/2012) revision b (06/2012) updated figure 16-1; removed figure 16-8; added new figure 16-8; replaced figures 16-9 and 16-10; added note 1 to figure 16-12; added note 3 to register 16-1; added note 4 to register 16-7; updated the electrical specifications section; other minor corrections.
pic16(l)f1512/3 ds41624b-page 338 preliminary ? 2012 microchip technology inc. notes:
? 2012 microchip technology inc. preliminary ds41624b-page 339 pic16(l)f1512/3 index a a/d specifications.................................................... 312, 313 aadacq register ............................................................ 158 aadcap register............................................................. 159 aadcon0 register .......................................................... 153 aadcon1 register .......................................................... 154 aadcon2 register .......................................................... 155 aadcon3 register .......................................................... 156 aadgrd register ............................................................ 158 aadpre register............................................................. 157 aadresxh register (adfm = 0)............................. 160, 161 aadresxl register (adfm = 0) ............................. 160, 161 absolute maximum ratings .............................................. 293 ac characteristics industrial and extended ............................................ 306 load conditions ........................................................ 305 ackstat ......................................................................... 218 ackstat status flag ...................................................... 218 adc .................................................................................. 129 acquisition requirements ......................................... 140 associated registers.......................................... 142, 162 automated automated capacitive voltage divider ... 146 block diagram........................................................... 130 calculating acquisition time..................................... 140 capacitive voltage divider (cvd)............................. 143 channel selection..................................................... 131 configuration............................................................. 131 configuring interrupt ................................................. 135 conversion clock.............................................. 131, 143 conversion procedure .............................................. 135 internal sampling switch (r ss ) i mpedance .............. 140 interrupts................................................................... 133 operation .................................................................. 134 operation during sleep ............................................ 134 port configuration ..................................................... 131 reference voltage (v ref )......................................... 131 source impedance.................................................... 140 special event trigger................................................ 134 starting an a/d conversion .............................. 133, 145 adcon0 register....................................................... 26, 136 adcon1 register....................................................... 26, 137 addfsr ........................................................................... 283 addwfc .......................................................................... 283 adres0h register (adfm = 0) ....................................... 138 adres0h register (adfm = 1) ....................................... 139 adres0l register (adfm = 0)........................................ 138 adres0l register (adfm = 1)........................................ 139 adresh register............................................................... 26 adresl register ............................................................... 26 adstat register ............................................................. 157 alternate pin function....................................................... 106 analog-to-digital converter. see adc ansela register ............................................................. 109 anselb register ............................................................. 113 anselc register ............................................................. 116 apfcon register....................................................... 27, 106 assembler mpasm assembler................................................... 324 b baudcon register.......................................................... 258 bf ............................................................................. 218, 220 bf status flag .......................................................... 218, 220 block diagrams .............................................................................. 10, 14 (ccp) capture mode operation ............................... 238 adc .......................................................................... 130 adc transfer function............................................. 141 analog input model................................................... 141 ccp pwm ................................................................ 242 clock source .............................................................. 44 compare................................................................... 240 crystal operation.................................................. 46, 47 eusart receive ..................................................... 248 eusart transmit .................................................... 247 external rc mode ...................................................... 47 fail-safe clock monitor (fscm)................................. 54 generic i/o port........................................................ 105 interrupt logic............................................................. 67 on-chip reset circuit................................................. 59 package diagram pic16(l)f1512/3 .................................................. 4 resonator operation .................................................. 46 timer0 ...................................................................... 163 timer1 ...................................................................... 167 timer1 gate.............................................. 172, 173, 174 timer2 ...................................................................... 179 voltage reference.................................................... 125 borcon register.............................................................. 61 bra .................................................................................. 284 break character (12-bit) transmit and receive ............... 267 brown-out reset (bor)...................................................... 61 specifications ........................................................... 310 timing and characteristics ....................................... 309 c c compilers mplab c18.............................................................. 324 call................................................................................. 285 callw ............................................................................. 285 capture module. see capture/compare/pwm(ccp) capture/compare/pwm ................................................... 237 capture/compare/pwm (ccp) ........................................ 238 associated registers w/ pwm ................................. 245 capture mode........................................................... 238 ccpx pin configuration............................................ 238 compare mode......................................................... 240 ccpx pin configuration.................................... 240 software interrupt mode ........................... 238, 240 special event trigger ....................................... 240 timer1 mode resource .................................... 240 prescaler .................................................................. 238 pwm mode duty cycle ........................................................ 243 effects of reset ................................................ 245 example pwm frequencies and resolutions, 20 mhz................................ 244 example pwm frequencies and resolutions, 8 mhz .................................. 244 operation in sleep mode.................................. 245 resolution ........................................................ 244 system clock frequency changes .................. 245 pwm operation ........................................................ 242 pwm overview......................................................... 242 pwm period ............................................................. 243 pwm setup .............................................................. 243
pic16(l)f1512/3 ds41624b-page 340 preliminary ? 2012 microchip technology inc. specifications............................................................ 312 ccp. see capture/compare/pwm ccpxcon (ccpx) register.............................................. 246 clock accuracy with asynchronous operation ................. 256 clock sources external modes ........................................................... 45 ec ....................................................................... 45 hs ....................................................................... 45 lp........................................................................ 45 ost..................................................................... 46 rc....................................................................... 47 xt ....................................................................... 45 internal modes ............................................................ 48 hfintosc.......................................................... 48 internal oscillator clock switch timing............... 49 lfintosc .......................................................... 48 clock switching................................................................... 51 code examples a/d conversion ................................................. 135, 152 changing between capture prescalers .................... 238 initializing porta..................................................... 105 writing to flash program memory .............................. 98 comparators c2out as t1 gate ................................................... 169 compare module. see capture/compare/pwm (ccp) config1 register.............................................................. 38 config2 register.............................................................. 40 core function register ....................................................... 25 customer change notification service ............................. 345 customer notification service........................................... 345 customer support ............................................................. 345 d data memory....................................................................... 18 dc and ac characteristics ............................................... 321 dc characteristics extended and industrial ............................................ 302 industrial and extended ............................................ 295 device configuration........................................................... 37 code protection .......................................................... 41 configuration word ..................................................... 37 user id .................................................................. 41, 42 device id register .............................................................. 42 device overview ............................................................. 9, 85 e eedatl register.............................................................. 102 effects of reset pwm mode ............................................................... 245 electrical specifications .................................................... 293 enhanced mid-range cpu .................................................. 13 enhanced universal synchronous asynchronous receiver transmitter (eusart)............................... 247 errata .................................................................................... 8 eusart............................................................................ 247 associated registers baud rate generator........................................ 260 asynchronous mode ................................................. 249 12-bit break transmit and receive................... 267 associated registers receive..................................................... 255 transmit .................................................... 251 auto-wake-up on break.................................... 265 baud rate generator (brg)............................. 259 clock accuracy ................................................. 256 receiver............................................................ 252 setting up 9-bit mode with address detect ...... 254 transmitter ....................................................... 249 baud rate generator (brg) auto baud rate detect..................................... 264 baud rate error, calculating............................ 259 baud rates, asynchronous modes .................. 261 formulas........................................................... 260 high baud rate select (brgh bit) .................. 259 synchronous master mode............................... 268, 272 associated registers receive .................................................... 271 transmit.................................................... 269 reception ......................................................... 270 transmission .................................................... 268 synchronous slave mode associated registers receive .................................................... 273 transmit.................................................... 272 reception ......................................................... 273 transmission .................................................... 272 extended instruction set addfsr................................................................... 283 f fail-safe clock monitor ...................................................... 54 fail-safe condition clearing....................................... 54 fail-safe detection ..................................................... 54 fail-safe operation..................................................... 54 reset or wake-up from sleep .................................... 54 firmware instructions ....................................................... 279 fixed voltage reference (fvr)........................................ 125 associated registers ................................................ 126 flash program memory ...................................................... 89 associated registers ................................................ 104 configuration word w/ flash program memory........ 104 erasing ....................................................................... 93 modifying .................................................................... 99 write verify ............................................................... 101 writing ........................................................................ 95 fsr register ...................................................................... 25 fvrcon (fixed voltage reference control) register..... 126 i i 2 c mode (mssp) acknowledge sequence timing ............................... 222 bus collision during a repeated start condition................... 227 during a stop condition ................................... 228 effects of a reset ..................................................... 223 i 2 c clock rate w/brg.............................................. 230 master mode operation.......................................................... 214 reception ......................................................... 220 start condition timing .............................. 216, 217 transmission .................................................... 217 multi-master communication, bus collision and arbitration ......................................................... 223 multi-master mode .................................................... 223 read/write bit information (r/w bit)........................ 199 slave mode transmission .................................................... 204 sleep operation........................................................ 223 stop condition timing .............................................. 222 indf register ..................................................................... 25 indirect addressing ............................................................. 33 instruction format............................................................. 280
? 2012 microchip technology inc. preliminary ds41624b-page 341 pic16(l)f1512/3 instruction set ................................................................... 279 addlw ..................................................................... 283 addwf..................................................................... 283 addwfc .................................................................. 283 andlw ..................................................................... 283 andwf..................................................................... 283 bra........................................................................... 284 call ......................................................................... 285 callw...................................................................... 285 lslf ......................................................................... 287 lsrf......................................................................... 287 movf........................................................................ 287 moviw ..................................................................... 288 movlb ..................................................................... 288 movwi ..................................................................... 289 option .................................................................... 289 reset ...................................................................... 289 subwfb................................................................... 291 tris.......................................................................... 292 bcf........................................................................... 284 bsf ........................................................................... 284 btfsc ...................................................................... 284 btfss ...................................................................... 284 call ......................................................................... 285 clrf......................................................................... 285 clrw ....................................................................... 285 clrwdt................................................................... 285 comf ....................................................................... 285 decf ........................................................................ 285 decfsz.................................................................... 286 goto ....................................................................... 286 incf.......................................................................... 286 incfsz ..................................................................... 286 iorlw ...................................................................... 286 iorwf ...................................................................... 286 movlw .................................................................... 288 movwf .................................................................... 288 nop .......................................................................... 289 retfie ..................................................................... 290 retlw ..................................................................... 290 return ................................................................... 290 rlf ........................................................................... 290 rrf........................................................................... 291 sleep ...................................................................... 291 sublw ..................................................................... 291 subwf ..................................................................... 291 swapf ..................................................................... 292 xorlw..................................................................... 292 xorwf..................................................................... 292 intcon register................................................................ 72 internal oscillator block intosc specifications.................................................... 307 internal sampling switch (r ss ) i mpedance ...................... 140 internet address................................................................ 345 interrupt-on-change ......................................................... 121 associated registers ................................................ 124 interrupts............................................................................. 67 adc .......................................................................... 135 associated registers w/ interrupts............................... 77 configuration word w/ clock sources ........................ 57 configuration word w/ ldo ........................................ 83 tmr1 ........................................................................ 171 intosc specifications ..................................................... 307 iocaf register................................................................. 123 iocan register ................................................................ 123 iocap register ................................................................ 123 l lata register .......................................................... 109, 115 latb register .................................................................. 112 load conditions................................................................ 305 low-power brown-out reset (lpbor) .............................. 62 lslf ................................................................................. 287 lsrf ................................................................................ 287 m master synchronous serial port. see mssp mclr ................................................................................. 62 internal........................................................................ 62 memory organization ......................................................... 15 data ............................................................................ 18 program...................................................................... 15 microchip internet web site.............................................. 345 moviw ............................................................................. 288 movlb ............................................................................. 288 movwi ............................................................................. 289 mplab asm30 assembler, linker, librarian ................... 324 mplab integrated development environment software.. 323 mplab pm3 device programmer .................................... 326 mplab real ice in-circuit emulator system ................ 325 mplink object linker/mplib object librarian ................ 324 mssp ............................................................................... 183 i 2 c mode .................................................................. 194 i 2 c mode operation.................................................. 196 spi mode.................................................................. 186 sspbuf register..................................................... 189 sspsr register ....................................................... 189 o opcode field descriptions............................................. 279 option ............................................................................ 289 option_reg register.................................................... 165 osccon register.............................................................. 56 oscillator associated registers.................................................. 57 oscillator module ................................................................ 43 ech ............................................................................ 43 ecl............................................................................. 43 ecm............................................................................ 43 hs............................................................................... 43 intosc ...................................................................... 43 lp ............................................................................... 43 rc .............................................................................. 43 xt ............................................................................... 43 oscillator parameters ....................................................... 307 oscillator specifications.................................................... 306 oscillator start-up timer (ost) specifications ........................................................... 310 oscillator switching fail-safe clock monitor .............................................. 54 two-speed clock start-up ......................................... 52 oscstat register ............................................................ 57 p packaging......................................................................... 327 marking............................................................. 327, 328 pdip details ............................................................. 328 pcl and pclath............................................................... 14 pcl register ...................................................................... 25 pclath register ............................................................... 25
pic16(l)f1512/3 ds41624b-page 342 preliminary ? 2012 microchip technology inc. pcon register ............................................................. 26, 65 pie1 register ................................................................ 26, 73 pie2 register ................................................................ 26, 74 pinout descriptions .................................................................................... 11 pir1 register................................................................ 26, 75 pir2 register................................................................ 26, 76 pmadr registers ............................................................... 89 pmadrh registers ............................................................ 89 pmadrl register............................................................. 102 pmadrl registers ............................................................. 89 pmcon1 register ...................................................... 89, 103 pmcon2 register ...................................................... 89, 104 pmdath register............................................................. 102 porta.............................................................................. 107 ansela register ..................................................... 107 associated registers ................................................ 110 configuration word w/ porta ................................. 110 porta register ................................................... 26, 27 specifications............................................................ 308 porta register ............................................................... 108 portb.............................................................................. 111 anselb register ..................................................... 111 associated registers ................................................ 113 portb register ................................................... 26, 27 portb register ............................................................... 112 portc.............................................................................. 114 anselc register ..................................................... 114 associated registers ................................................ 116 portc register ................................................... 26, 27 portc register ............................................................... 115 porte.............................................................................. 117 associated registers ................................................ 119 configuration word w/porte .................................. 119 porte register ......................................................... 26 porte register ............................................................... 118 power-down mode (sleep) ................................................. 79 associated registers .................................................. 82 power-on reset .................................................................. 60 power-up time-out sequence ............................................ 62 power-up timer (pwrt)..................................................... 60 specifications............................................................ 310 pr2 register....................................................................... 26 precision internal oscillator parameters........................... 307 program memory ................................................................ 15 map and stack (pic12f/lf1840) ............................... 17 map and stack (pic16(l)f1512) ................................ 16 map and stack (pic16f1936/lf1936, pic16f1937/lf1937) ......................................... 16 programming, device instructions .................................... 279 r rcreg ............................................................................. 254 rcreg register................................................................. 27 rcsta register.......................................................... 27, 257 reader response ............................................................. 346 read-modify-write operations.......................................... 279 registers aadacq (adc acquisition time control) ................ 158 aadcap (adc add. sample cap. selection) .......... 159 aadcon0 (adc control 0) ...................................... 153 aadcon1 (adc control 1) ...................................... 154 aadcon2 (adc control 2) ...................................... 155 aadcon3 (adc control 3) ...................................... 156 aadgrd (adc guard ring control)........................ 158 aadpre (adc pre-charge)..................................... 157 aadresxh (adc result high) with adfm = 0) .................................................................. 160, 161 aadresxl (adc result low) with adfm = 0) 160, 161 adcon0 (adc control 0) ........................................ 136 adcon1 (adc control 1) ........................................ 137 adres0h (adc result high) with adfm = 0) ........ 138 adres0h (adc result high) with adfm = 1) ........ 139 adres0l (adc result low) with adfm = 0).......... 138 adres0l (adc result low) with adfm = 1).......... 139 adstat (adc status) ............................................. 157 ansela (porta analog select)............................. 109 anselb (portb analog select)............................. 113 anselc (portc analog select) ............................ 116 apfcon (alternate pin function control) ............... 106 baudcon (baud rate control)............................... 258 borcon brown-out reset control) .......................... 61 ccpxcon (ccpx control) ....................................... 246 configuration word 1.................................................. 38 configuration word 2.................................................. 40 core function, summary............................................ 25 device id .................................................................... 42 eedatl (eeprom data) ........................................ 102 fvrcon................................................................... 126 intcon (interrupt control)......................................... 72 iocaf (interrupt-on-change porta flag).............. 123 iocan (interrupt-on-change porta negative edge)................................................. 123 iocap (interrupt-on-change porta positive edge) .................................................. 123 lata (data latch porta)....................................... 109 latb (data latch portb)....................................... 112 latc (data latch portc) ...................................... 115 option_reg (option) ......................................... 165 osccon (oscillator control) ..................................... 56 oscstat (oscillator status) ..................................... 57 pcon (power control) ............................................... 65 pie1 (peripheral interrupt enable 1)........................... 73 pie2 (peripheral interrupt enable 2)........................... 74 pir1 (peripheral interrupt register 1) ........................ 75 pir2 (peripheral interrupt request 2) ........................ 76 pmadrl (program memory address) ..................... 102 pmcon1 (program memory control 1).................... 103 pmcon2 (program memory control 2).................... 104 pmdath (program memory data)........................... 102 porta ..................................................................... 108 portb ..................................................................... 112 portc ..................................................................... 115 porte ..................................................................... 118 rcreg..................................................................... 264 rcsta (receive status and control) ...................... 257 spbrgh .................................................................. 259 spbrgl ................................................................... 259 special function, summary........................................ 26 sspadd (mssp address and baud rate, i 2 c mode) ......................................................... 235 sspcon1 (mssp control 1) ................................... 232 sspcon2 (ssp control 2) ...................................... 233 sspcon3 (ssp control 3) ...................................... 234 sspmsk (ssp mask)............................................... 235 sspstat (ssp status)............................................ 231 status ..................................................................... 19 t1con (timer1 control) .......................................... 175 t1gcon (timer1 gate control)............................... 176 t2con ..................................................................... 181 trisa (tri-state porta)......................................... 108
? 2012 microchip technology inc. preliminary ds41624b-page 343 pic16(l)f1512/3 trisb (tri-state portb)......................................... 112 trisc (tri-state portc) ........................................ 115 trise (tri-state porte)......................................... 118 txsta (transmit status and control) ...................... 256 vregcon (voltage regulator control) ..................... 81 wdtcon (watchdog timer control) ......................... 87 wpub (weak pull-up portb) ................................. 113 reset .............................................................................. 289 reset................................................................................... 59 reset instruction ................................................................. 62 resets................................................................................. 59 associated registers .................................................. 66 revision history ................................................................ 337 s software simulator (mplab sim)..................................... 325 spbrg register ................................................................. 27 spbrgh register ............................................................ 259 spbrgl register ............................................................. 259 special event trigger........................................................ 134 special function registers (sfrs)..................................... 26 spi mode (mssp) associated registers ................................................ 193 spi clock .................................................................. 189 sspadd register............................................................. 235 sspcon1 register .......................................................... 232 sspcon2 register .......................................................... 233 sspcon3 register .......................................................... 234 sspmsk register............................................................. 235 sspov.............................................................................. 220 sspov status flag .......................................................... 220 sspstat register ........................................................... 231 r/w bit...................................................................... 199 stack ................................................................................... 31 accessing.................................................................... 31 reset........................................................................... 33 stack overflow/underflow................................................... 62 status register ............................................................... 19 subwfb........................................................................... 291 t t1con register ......................................................... 26, 175 t1gcon register............................................................. 176 t2con (timer2) register ................................................. 181 t2con register ................................................................. 26 temperature indicator associated registers ................................................ 128 temperature indicator module .......................................... 127 thermal considerations.................................................... 304 timer0............................................................................... 163 associated registers ................................................ 165 operation .................................................................. 163 specifications............................................................ 311 timer1............................................................................... 167 associated registers.................................................. 177 asynchronous counter mode ................................... 169 reading and writing ......................................... 169 clock source selection............................................. 168 interrupt..................................................................... 171 operation .................................................................. 168 operation during sleep ............................................ 171 prescaler................................................................... 169 secondary oscillator................................................. 169 specifications............................................................ 311 timer1 gate selecting source............................................... 169 tmr1h register....................................................... 167 tmr1l register ....................................................... 167 timer2 .............................................................................. 179 associated registers ................................................. 182 timer2/4/6 associated registers ................................................. 182 timers timer1 t1con ............................................................. 175 t1gcon........................................................... 176 timer2 t2con ............................................................. 181 timing diagrams a/d conversion ........................................................ 313 a/d conversion (sleep mode).................................. 314 acknowledge sequence ........................................... 222 asynchronous reception.......................................... 254 asynchronous transmission .................................... 250 asynchronous transmission (back to back) ............ 251 auto wake-up bit (wue) during normal operation. 266 auto wake-up bit (wue) during sleep .................... 266 automatic baud rate calibration ............................. 264 baud rate generator with clock arbitration............. 215 brg reset due to sda arbitration during start condition.................................................. 226 brown-out reset (bor)............................................ 309 brown-out reset situations ........................................ 61 bus collision during a repeated start condition (case 1)............................................................ 227 bus collision during a repeated start condition (case 2)............................................................ 227 bus collision during a start condition (scl = 0) ..... 226 bus collision during a stop condition (case 1)....... 228 bus collision during a stop condition (case 2)....... 228 bus collision during start condition (sda only) ...... 225 bus collision for transmit and acknowledge ........... 224 capture/compare/pwm (ccp) ................................ 312 clkout and i/o ...................................................... 307 clock synchronization .............................................. 212 clock timing............................................................. 306 fail-safe clock monitor (fscm)................................. 55 first start bit timing ................................................. 216 i 2 c bus data............................................................. 319 i 2 c bus start/stop bits ............................................. 318 i 2 c master mode (7 or 10-bit transmission) ............ 219 i 2 c master mode (7-bit reception) .......................... 221 i 2 c stop condition receive or transmit mode......... 223 int pin interrupt ......................................................... 70 internal oscillator switch timing ................................ 50 repeat start condition ............................................. 217 reset start-up sequence ........................................... 63 reset, wdt, ost and power-up timer ................... 308 send break character sequence............................. 267 spi master mode (cke = 1, smp = 1) ..................... 316 spi mode (master mode) ......................................... 189 spi slave mode (cke = 0) ....................................... 317 spi slave mode (cke = 1) ....................................... 317 synchronous reception (master mode, sren) ....... 271 synchronous transmission ...................................... 269 synchronous transmission (through txen) ........... 269 timer0 and timer1 external clock ........................... 311 timer1 incrementing edge ....................................... 171 two speed start-up.................................................... 53 usart synchronous receive (master/slave) ......... 315 usart synchronous transmission (master/slave). 314
pic16(l)f1512/3 ds41624b-page 344 preliminary ? 2012 microchip technology inc. wake-up from interrupt ............................................... 80 timing parameter symbology........................................... 305 timing requirements i 2 c bus data ............................................................. 320 spi mode .................................................................. 318 tmr0 register .................................................................... 26 tmr1h register ................................................................. 26 tmr1l register .................................................................. 26 tmr2 register .................................................................... 26 tris .................................................................................. 292 trisa register ........................................................... 26, 108 trisb................................................................................ 111 trisb register ........................................................... 26, 112 trisc ............................................................................... 114 trisc register ........................................................... 26, 115 trise................................................................................ 117 trise register ........................................................... 26, 118 two-speed clock start-up mode ........................................ 52 txreg.............................................................................. 249 txreg register ................................................................. 27 txsta register .......................................................... 27, 256 brgh bit .................................................................. 259 u usart synchronous master mode requirements, synchronous receive............... 315 requirements, synchronous transmission ...... 315 timing diagram, synchronous receive............ 315 timing diagram, synchronous transmission ... 314 v v ref . s ee adc reference voltage vregcon register............................................................ 81 w wake-up on break ............................................................ 265 wake-up using interrupts ................................................... 80 watchdog timer (wdt) ...................................................... 62 associated registers .................................................. 88 modes ......................................................................... 86 specifications............................................................ 310 wcol ....................................................... 215, 218, 220, 222 wcol status flag .................................... 215, 218, 220, 222 wdtcon register.............................................................. 87 wpub register ................................................................. 113 write protection................................................................... 41 www address.................................................................. 345 www, on-line support........................................................ 8
? 2012 microchip technology inc. preliminary ds41624b-page 345 pic16(l)f1512/3 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
pic16(l)f1512/3 ds41624b-page 346 preliminary ? 2012 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds41624b pic16(l)f1512/3 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2012 microchip technology inc. preliminary ds41624b-page 347 pic16(l)f1512/3 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: pic16f1512, pic16lf1512 pic16f1513, pic16lf1513 tape and reel option: blank = standard packaging (tube or tray) t = tape and reel (1) temperature range: i= -40 ? c to +85 ? c(industrial) e= -40 ? c to +125 ? c (extended) package: mv = micro lead frame (uqfn) 4x4 p = plastic dip (pdip) so = soic sp = skinny plastic dip (spdip) ss = ssop pattern: qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic16f1512t - i/so 301 tape and reel, industrial temperature, soic package b) pic16f1512 - i/p industrial temperature pdip package c) pic16f1513 - e/ss extended temperature, ssop package note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. [x] (1) tape and reel option -
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